Moores Law

Eric Swanson
15. Moore's Law
Call me a heretic, but in the late 1970s, long before I'd heard of Philbrick,
Widlar, or Gilbert, I learned about Moore's Law. Gordon Moore came
down to a VLSI conference at Caltech armed with a "moon curve" somewhat like that shown in Figure 15-1. His message was simple: memory
density increases fourfold every three years. Run the linear-year versus
log-density curve out for a couple of decades, and you reach levels of
integration so fabulous that you might as well be at the moon,
Moore also claimed that increases in memory density trickle down to
less significant areas like microprocessors, and he challenged the design
community to try to figure out what on earth to do with all those extra
transistors. Fifteen years later, the minicomputer is dead, Moore's Intel is
very big, and, just like clockwork, memories are a thousand times denser.
The analog-oriented readers of this book may appreciate the following
memory aids. Chip complexity increases 4X every three years, 12dB
every three years, 4dB/year, 40dB/decade. Integration, it seems, is a
second-order high-pass filter.
Figure 15-1.
A moon curve.
1980
2000
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lloore's Law
For me, learning Moore's Law before moving on to analog circuits
proved very helpful. Moore's Law gives digital designers a drive to obsolete the past, and to do so quickly. A 64K DRAM designer knew better
than to rest on his laurels, lest Moore's Law run him over. Young digital
designers know that their first chips must whip the old guys' chips. In
contrast, the analog design community takes the view that its new kids
may approach, with time, the greatness of the old guys. That view is
wrong; our expectations for young designers should be set much higher.
Fortunately, a good-sized piece of the analog 1C business now follows
Moore's Law. State-of-the-art mixed-signal circuits crossed the VLSI
threshold of 10000 transistors around 1985. A decade later we're at the
million-transistor level. Has the analog design business fundamentally
changed? Are we reduced to button-pushing automatons? Is elegance
gone?
The next three sections attempt to answer such questions. First, we
take a look at some of the competition between brute-force integration
and design elegance. Elegance lives on, but brute force must be respected!
Next, we look at a few of the interesting subcircuits of analog CMOS.
True to the analog tradition, state-of-the-art subcircuits are born in the
brain or in the lab, not on the workstation, never synthesized. Finally,
we'll look at elegance at a different level, how analog circuits with thousands of transistors can have legitimate elegance of their own.
Brute Force vs. Elegance
The evolution of analog-to-digital converters bears an interesting relationship to Moore's Law. Figure 15-2 plots the dynamic range of
state-of-the-art analog-to-digital converters as a function of their sampling frequency. Over many decades of ADC speed, the world's best
converter performance falls on a reasonably well-defined line. The line
doesn't stand still over the years; it moves upward. The rate of improvement has remained remarkably constant since the first monolithic converters appeared in the mid 1970s. Transistors get faster and more numerous.
CMOS technology rises to compete with bipolar. Power supply and signal
voltages decrease. New architectures emerge and are perfected. And converter performance improves by a very predictable 2dB/year.
Analog-to-digital converters are noisy by analog signal processing
standards. Today's world-class converters have input-referred noise spectral densities of 100nV/VHz or so. Perhaps ADC evolution will stop
when converters reach the noise performance of, say, 50£1 resistors, but
we won't reach such quasi-fundamental limits for a generation! Also, no
matter how noisy analog-to-digital converters may be, they represent the
only path from the analog world to decent-quality memory.
What's the tie-in to Moore's Law? The Law gives us a 4X increase in
ADC complexity every three years. We can take it easy for the next three
years and simply integrate four of today's converters on a common sub252
Eric Swanson
160 r-
Figure 15-2,
Monolithic ADC
performance 1993.
—ADCs
- -50 ohm noise
101
102
103
104
105
106
107
sampling frequency (Hz)
strate. We'll connect the same analog signal to all four converter inputs
and design some simple logic to add the four digital outputs every sampling .'period. If each converter's noise is dominated by thermal noise (uncorrelsted from converter to converter), we get a 6dB improvement in
dynamic range. The Moore's Law increase in integration underpins ADC
improvement of 2dB/year!
To my knowledge, brute-force replication of ADCs has never yielded
a converter of world-class performance. World-class converters exploit
design cleverness to achieve lower manufacturing costs than brute-force
alternatives. Yet the brute-force option serves as a competitive reminder
to clever engineers—they had better not take too long to perfect their
cleverness!
Born in the Lab
Certainly, the complexity of analog VLSI demands computer circuit simulation. Circuit simulation hasn't changed much over the years. Perhaps
the only significant progress in this area comes from better computers.
Solving big, nonlinear differential equations is still, after all, solving big,
nonlinear differential equations. CAD tool vendors, ever-notorious for
overhyping their products, claim that improved graphics interfaces translate into huge productivity increases, but in practice these interfaces add
little. Now-obsolete batch-mode tools forced designers to think before
simulation, and thinking is a very healthy thing. Today's 17-inch workstation monitors cannot display enough detail, nowhere near as much as
yesterday's quarter-inch-thick printouts, and engineers must constantly
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Moore's Law
page from screen to screen. Graphics interfaces may be sexy and fun, but
real progress comes from MIPS.
Young engineers sometimes fall into the trap of thinking that computer
simulations define reality. They cannot finalize a design before the simulations work. Unfortunately for them, certain problems that real circuits
handle easily are very difficult for simulators. Charge conservation, critical to analog CMOS design, is one such problem. When your simulator
loses charge in a way that the real circuit cannot, it's time to discount the
error and move on. The integrated circuit business is paid to ship real
chips, not to have simulations match reality. The most valuable design
experience related to simulation is to be comfortable with its limitations!
The best analog VLSI subcircuits are born in the lab. Two of my favorites appear below. The first involves a phenomenon not even modeled
in SPICE, and the second looks at linearity levels so extreme that simulation will probably never be relevant.
I've always been amused that the most accurate low-speed analog-todigital converters are built from solid-state electronics' most miserable
low-frequency devices. Actually, that overstates the case. GaAs MESFETs
are even worse than silicon MOSFETs, but CMOS devices are pretty bad.
Start with poor device matching, maybe 10X worse than bipolar. Add in
huge doses of 1/f noise. Complete the recipe with the power supply, temperature, and impedance sensitivities of charge injection. Small wonder
the old bipolar companies thought they needed biCMOS to do anything
useful! They were wrong; few state-of-the-art converters ever use
biCMOS. Moore's Law is enough.
Dave Welland's self-calibrated CS5016 contains wonderful architecture. The 5016 is a 16-bit, 50kHz, successive-approximation converter
whose architecture dates back to 1984, building on early self-calibration
work done by Dave Hodges and Hae-Seung Lee at Berkeley. All of these
folks recognized the fact that, given enough transistors, an analog-todigital converter could figure out all by itself how to divide up a reference voltage into precisely equal pieces. The principle may be obvious,
but the death is in the details. Noise constantly creeps in to corrupt the
measurement of all those little pieces, and the effects of noise must be
removed just right.
Once the DAC inside the ADC is properly calibrated, the comparator
is all that's left. Everyone knows that 1/f noise in the comparator is bad
news. While CMOS 1/f noise is bad, it's always eliminated by either
autozeroing or chopping, and by now it's axiomatic in the design business
that one of those two techniques can be counted on for any analog VLSI
application. The 5016 autozeroes its comparator in a way we'll describe
later.
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Eric Swarsson
A less-appreciated requirement for the comparator inside an SAR
ADC is that it had better be memoryless. For some analog inputs, the
successive-approximation algorithm requires the comparator to make its
most sensitive decision in the approximation cycle immediately following
huge comparator overdrive. If the comparator has any memory at all,
missing codes can result.
Sure enough, when the 5016 silicon debugging reached Dave's original design intent, we began to see the telltale fingerprints of comparator
memory. And not just your basic thermal-Induced memory. These memory symptoms disappeared at high temperature and were far worse at low
temperature. Slowing down the chip's master clock provided alarmingly
little benefit. Something strange was happening, and it surely wasn't
modeled in SPICE.
While Dave worked to characterize the problem on the 5016 probe
station, I decided to build the NMOS differential amplifier shown in
Figure 15-3. This decision was fortunate, because the ancient discrete
MOSFETs I used (3N169s) had about 5 times the memory of Orbit
Semiconductor's Sum MOSFETs. Simple Siliconix transmission gates
moved the differential pair from huge overdrive to zero overdrive, and the
results are shown in Figures 15-4 and 15-5. The MOSFET which carries
the most current during overdrive experiences a temporary threshold voltage increase. When the differential pair is returned to balance at the input,
the output exhibits a nasty, long recovery tail. Soak the differential pair in
V DD =10V
Figure 15-3.
Memory test circuit.
VBIAS
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Moore's Law
CLK1 5V/div
¥OOT SGGuV/cfiv
Figure 15-4.
Memory of negative overdrive (Vj =
5V,V2 = 3V).
Figure 15-5.
Memory of positive
overdrive (Vt = 5V,
V2 = 7V).
the overdriven state for 2x longer, and the lifetime of the recovery tail
increases by 1.5x. Increase the magnitude of the overdrive beyond the
point where all of the diffpair current is switched, and the shape of the tail
stops changing.
I figured that some sort of equilibrium between fixed charges and mobile charges at the Si-SiO2 interface had to be involved. At high temperatures this equilibrium could be re-established in much less time than one
comparison cycle, but at low temperatures recovery could be slow. Everlonger "soak times" would allow ever-slower fixed-charge states to participate in the threshold shift. Since the fixed-charge population could never
significantly reduce the mobile carrier population in the channel, saturation of the memory effect would occur once all of the mobile carriers
were switched during overdrive. The story seemed to hang together.
Well, venture-capital-funded startups don't survive based on stories,
they survive based on fixes. You might not believe me if I told you what I
was doing when I came up with the fix, but rest assured I wasn't pushing
buttons on a workstation! Anyway, I guessed that if I could accumulate
the surfaces of the diffpair MOSFETs, pull their channel voltages much
higher than their gates, then I could change the hole concentrations at
their Si-SiO2 interfaces by maybe eighteen orders of magnitude, and
CLK1 5V/div
500uV/div
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Eric Swanson
Figure 15-6.
Erasure test circuit.
V
erase that memory. The next day I built the circuit of Figure 15-6 and
used it to produce the photographs of Figures 15-7 and 15-8. Only a few
nanoseconds of flush time were required to completely erase the differential pair's memory. It may seem like a strange thing to do to a precision
comparator, but we've shipped a lot of product with flushed MOSFETs.
OUT
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Moore's Law
CLK1 5V/div
VOUT SOQuV/div
CLK2 5V/div
Figure 15-6.
Erased positive
overdrive (V1 = 5V,
V2 = 7V).
Sampling the Input
When I interviewed at Crystal Semiconductor in 1984,1 thought that selfcalibration was the greatest thing since sliced bread and that customers
would love it. Wrong. Customers loved the accuracy of calibrated parts,
but they hated to calibrate to get it. If I had been managing the 5016 development, I wouldn't have paid much attention to post-calibration temperature and power-supply shifts. Now I know better. The true quality of a
self-calibrated design is best measured by how stable its performance is
without recalibration. Fortunately, Dave Welland was way ahead of me
there.
A conceptual view of the 5016 sampling path appears in Figure 15-9.
The comparator input stage is used as part of an op amp during signal
acquisition. This neatly autozeroes the stage's 1/f noise when we use it
during conversion. Dave recognized that the charge injection of the sampling switch adds error charge to the signal charge, and he minimized the
error in an ingenious way. Rather than using a conventional transmission
gate, Dave built a tri-state output stage into the closed-loop sampling
Figure 15-9.
CS5016 sampling
architecture.
VREF
-
Sampling
Switch
DAC
Switches
OUT
Comparator
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Eric Swanson
CDAC
To DAC
Switches
Figure 15-10,
CS5016 sampling
switch detail,
T = TRACK
H = HOLD
path. A simplified schematic is shown in Figure 15-10. The gate voltage
swings on the sampling devices are much smaller than those associated
with transmission gates, and the swings can be designed to be powersupply independent. Furthermore, at shutoff, most of the channel charge
of the active-region sampling MOSFETs flows out their sources and away
from CDAC. The results speak for themselves: the 5016's offset shifts
with temperature by less than .02LSB/°C.
More recently, the progress in open-loop sampling has been amazing.
Just about every commercial delta-sigma converter samples its analog
input with simple capacitor-transmission-gate structures. These open-loop
sample-holds help achieve overall converter linearities now surpassing
12CWB.1 Optimization of sampling circuit performance only involves a
few dozen transistors, and we're getting better all the time! Charge injection from the MOSFET is getting pretty well understood, but newcomers
should be forewarned that little of this understanding comes from the
Sparcstation!
Elegance a* a Higher Level
The real elegance of analog VLSI circuits occurs beyond the subcircuit
level. Suecessftil analog VLSI architectures trivialize all but a few of a
chip's analog subcircuits. Successful architectures are minimally analog.
Successful architects know digital signal processing. Analog VLSI circuits may be complex beasts, but when an architecture is really clean,
you know. Your competition knows, too, a few years down the road!
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Moore's Law
Digital Signal Processing
The journey was hectic but fun. Active-RC filters gave way to integrated
switched-capacitor filters. The switched-capacitor filters were noisy
compared to their active-RC predecessors, but you can't be expected
to work miracles with a mere -lOOOpF of total capacitance! Fortunately,
switched-capacitor filter characteristics stayed put, allowing them to dominate sensitivity-critical, noise-tolerant telecom applications.
Once Moore's Law gave us cheap enough digital transistors and cheap
enough data converters, the switched-capacitor technology was doomed.
Digital filters of wonderful precision have no sensitivity and no drift.
Their noise performance can be perfectly simulated, and you can ask all
the essential questions before silicon tapes out. Digital filters can be
tested with digital test vectors to quality levels unheard of in the analog
world. Analog chauvinists take heed: don't fight if you can't win.
Fortunately for us dinosaurs, analog design experience helps produce
better digital filters. Optimizing datapath wordwidths is very similar to
optimizing kT/C noise. Quantizing filter coefficients is similar to quantizing signals. Elegant, high-performance analog filter designs will always
be difficult to put into production, but once an elegant DSP design is
done, it's out of design forever. You can't beat that!
The power of digital signal processing is never more apparent than
when you're dealing with adaptive signal processing. Adaptive digital
filters, be they echo cancelers or data channel equalizers, are simply more
intelligent, more interesting, than their fixed-function predecessors. Take
the time to understand them, and you'll be hooked.
Noise and Robustness
Just about everyone who transmits digital bits tries to send those bits as
far as possible, as fast as possible, down the cheapest possible medium,
until recovery of those bits is an analog problem. Digital data detection is
one of the best long-term analog businesses there is. I'll add that nobody
is too enthusiastic about sending a clock alongside the data. Thus, timing
recovery is another of the great long-term analog businesses.
Data detection and timing recovery circuits were among the first to
embrace Moore's Law. Adaptive equalizers routinely clean up the frequency responses of real-world data channels. Maximum-likelihood
receivers figure out the most likely transmitted sequence despite a channel's additive noise. Error-correcting codes operate on the detected bit
sequence, often providing further orders-of-magnitude improvement in
system bit error rates. All of these techniques, originally perfected for
board-level designs, are found in abundance on today's AVLSI chips.
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Eric Swanson
Traditional analog signal processing carries with it a certain hopelessness with respect to noise. As analog processing complexity grows, additive noise sources grow in number, and system performance fades away.
Modern digital communication system designers must be forgiven if they
look at the weapons of the analog world and see Stone Age technology in
the Iron Age. Throwing rocks may still get the job done, but the weapons
of Moore's Law are elegant at a higher level.
The Elegance of Digital Audio
Audio data converters represent highly refined combinations of analog
and digital signal processing. Converter performance now surpasses what
reasonable people can claim to hear, and still it improves by 2dB/year.
Can this possibly make sense?
We all know that the great musical performances of our parents' generation are irrevocably lost. Lost by the limitations of recording electronics
of that era. Lost thanks to the deterioration of analog storage media. Lost
for a variety of technological reasons, but lost. Digital recording and storage now rale. The great sounds of our generation will never be lost. The
job is not finished. Combine a small array of microphones, very good
analog-to-digital converters, and digital signal processing, and the results
can be magic. We'll be able to listen in new ways, to hear the contributions of individuals to the sounds of their orchestras.
i. Don Kerth et al, "A 120dB Linear Switched-Capacitor Delta-Sigma Modulator,'
ISSCC Digest of Technical Papers (February 1994).
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