回路図（CPU

3
VDD_1
VDD_2
VDD_3
VDD_4
17
49
81
112
VSS_1
VSS_2
VSS_3
VSS_4
16
48
82
113
R6
R5
1.5K
5
6
7
R4
EXB-38V152JV
1
8
4
3
2
5
6
+5V
+3.3
VCC
CANH
7
6
CANH
CANL
CANL
TJA1040
5
2
SPLIT
R13
60.4
R14
60.4
1
2
3
1
2
3
CAN
Connector
56pF
STB
R15
0
MII_AVDD
JP1
DF1B_3P_2.5DSA
3
TXD
RXD
GND
8
TXP
TXN
RXP
R16
100
RXN
+1.8
LINK
J1
ACT
R17
240
TouchPanel
Connector
③　変更
U6
1
2
3
4
5
6
7
8
9
10
11
12
TD+
TDRD+
TCT
NC1
RDRCT
NC2
GA
GK
YK
YA
RJ45
Connector
HFJ11-2450E-L21
FPC4
CLK25
10pF
1
2
3
4
C26
1
2
3
4
10pF
LCD_TOP
LCD_LEFT
LCD_BOTTOM
LCD_RIGHT
STR912FAW44X6
CPU_GPIO[0..3]
R3
EXB-38V103JV
7
3
4
8
5
2
6
4
1
7
3
R2
EXB-38V103JV
8
2
1
2
CPU_LED
1
4
0.1uF
CPU_INTR
C
0.1uF
CPU_nWRL
40
50
MII_AVDD
L2
MMZ2012Y202B
内層プレーン
C25
CPU_nWRH
C17 0.1uF
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
C8
5
6
7
13
14
15
118
119
CPU_AD16
CPU_AD17
CPU_AD18
CPU_AD19
CPU_AD20
CPU_AD21
CPU_AD22
CPU_AD23
CPU_nRESET
39
45
62
+3.3
L1
MMZ2012Y202B
C24
CPU_ALE
MII_AVCC
+3.3
C23
CPU_nRD
U5
TJA1040
CAN_TXD
CAN_RXD
C18
CPU_nCS[0..3]
7
10
14
20
24
R7 10k
R8 10k
MII_TX_EN
STE100P
+3.3
C16 0.1uF
CPU_AD[0..23]
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
LED
64
63
0.1uF
8
24
56
72
87
40
105
121
29
31
19
20
83
84
92
93
LED1
MII_TX_CLK
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
C2
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
LCD_TOP
LCD_LEFT
LCD_BOTTOM
LCD_RIGHT
EXT_CONN4
EXT_CONN5
EXT_CONN6
EXT_CONN7
+3.3
CPU_JRTCK
CPU_nJTRST
CPU_JTCK
CPU_JTMS
CPU_JTDO
CPU_JTDI
C15 0.1uF
FPGA_IN[6..13]
P5.0
P5.1
PHYCLK_P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
9
13
16
17
22
53
55
56
57
58
52
54
0.1uF
9
23
57
73
86
43
102
120
12
18
25
27
70
77
79
80
MII_AVCC
MII_RX_CLK
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RX_ER
MII_RX_DV
49.9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
CAN_RXD
CAN_TXD
MII_PHYCLK
MII_TX_EN
CPU_nCS0
CPU_nCS1
CPU_nCS2
CPU_nCS3
①　変更
8
30
31
32
49
47
46
44
43
51
48
R12
122
4
123
39
MII_MDIO
USB_DN
USB_DP
nRESET
CPU_nRESET
CLK25
RX_CLK
RXD0
RXD1
RDX2
RDX3
GNDE
RX_ER/RXD4
TEST
RX_DV
PWRDWN
RESET
TX_CLK
RIP
TXD0
TXD1
NC_1
TXD2
NC_2
TXD3
NC_3
TX_ER/TXD4
NC_4
TX_EN
VCCA_1
CFG0
VCCA_2
CFG1
VCCA_3
VCCA_4
VCCE/I_1
VCCA_5
VCCE/I_2
VCCE/I_3
GNDA_1
GNDA_2
GNDE/I_1
GNDA_3
GNDE/I_2
GNDA_4
GNDA_5
C1
AVDD
AVSS
AVREF
VBATT
TXP
TXN
25
26
27
28
29
MII_INTR
MII_MDIO
MII_MDC
MII_COL
MII_CRS
49.9
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
21
23
nRESET
61
41
42
59
60
R11
3
2
1
128
127
126
125
124
RXP
RXN
TXP
TXN
+3.3
MDINT
MDIO
MDC
COL
CRS
240
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
X1
X2
19
18
LINK
ACT
C6 0.1uF
55
59
60
61
63
65
66
68
21
22
74
75
91
94
95
96
89
100
104
103
42
41
97
107
108
111
117
115
CPU_nWRL
CPU_nWRH
CPU_ALE
CPU_nRD
UART0_RXD
UART0_TXD
UART1_RXD
UART1_TXD
MII_INTR
CPU_INTR
CPU_LED
SD_WP
EMI_BWR_WRLn
EMI_WRHn
EMI_ALE
EMI_RDn
TAMPER_IN
MII_MDIO
USBDN
USBDP
RESET_INn
RESET_OUTn
X1_CPU
X2_CPU
X1_RTC
X2_RTC
JRTCK
JTRSTn
JTCK
JTMS
JTDO
JTDI
33
34
35
36
37
38
C5 0.1uF
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
USBCLK_P2.7
12
11
RXP
RXN
D
TEST_SE
LEDS
LEDC
LEDL
LEDTR
LEDR10
C4 0.1uF
10
11
33
35
37
45
53
54
MII_PHYCLK
C3 0.1uF
CPU_GPIO0
CPU_GPIO1
CPU_GPIO2
CPU_GPIO3
SSP0_SCLK
SSP0_MOSI
SSP0_MISO
SSP0_MSS
C14 0.1uF
STM1001TWX6F
1
R1 4.99K
CPU_AD8
CPU_AD9
CPU_AD10
CPU_AD11
CPU_AD12
CPU_AD13
CPU_AD14
CPU_AD15
MF0
MF1
MF2
MF3
MF4
FDE
IREF
330
46
47
50
51
52
58
62
64
5
4
3
2
1
6
15
+3.3
0.1uF
3
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
C13 0.1uF
1
VSS
0.1uF
RST
nRESET
C9
VCC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
C12 0.1uF
100K
U4
2
98
99
101
106
109
110
114
116
C22 0.1uF
C
R9
MII_RX_ER
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_COL
MII_CRS
MII_MDC
LCD_TOP
LCD_LEFT
LCD_BOTTOM
LCD_RIGHT
EXT_CONN0
EXT_CONN1
EXT_CONN2
EXT_CONN3
⑤　抵抗値変更
+3.3
CPU_AD0
CPU_AD1
CPU_AD2
CPU_AD3
CPU_AD4
CPU_AD5
CPU_AD6
CPU_AD7
C11 0.1uF
5
26
28
30
32
34
36
38
44
C21 0.1uF
NC
3
NC
4 CLK25
MII_RXD2
MII_RXD3
MII_RX_CLK
MII_RX_DV
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
C20 0.1uF
OUT
GND
ED
2
FXO-HC735-25
VDD
U3
1
U2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
C7
6
CLK25は短く、FPGAまでとCPUまでとが等長となるように
+3.3
U1
67
69
71
76
78
85
88
90
330nF
+3.3
+3.3
1
+3.3
C10 0.1uF
メタルマスクは
無修正になるように！
2
②　変更
C19 0.1uF
D
4
R10
5
修正
１．ＪＴＡＧコネクタのCPU_JRTCK配線
２．U2のPWRDWN変更
３．U6のTCT変更
４．U6コネクタ変更
５．R9抵抗値変更 330 ->100K
６．液晶のクロック独立 VGA_CLK2
７．液晶コネクタJ8 のアドレス配線変更（アドレス->上位６ビット）
８．液晶コネクタJ7 のアドレス配線変更
９．J19の19番ピン配線変更
10．J19の12番ピン配線変更
11．J14の7番ピン配線変更
MII_TX_CLK
12．電源スイッチSW1変更(IS1250)
SD_CD
MII_RXD0
13．15番ピン電源ＧＮＤ接続
MII_RXD1
④　変更
EXT_CONN[0..6]
B
B
+3.3
+3.3
1
3
2
DCD
DTR
DSR
TXD
RXD
RTS
CTS
10
13
14
15
16
17
NC
NC
NC
NC
NC
NC
6
GND
3
VBUS
D-
8
5
D+
4
NC
NC
NC
NC
NC
22
21
20
19
18
J4
USBminiB_CU0416SD
1
2
3
4
5
CON20
8
7
nRESET
1
28
27
26
25
24
23
7
JAG
Connector
6
10uF
C36
nRESET
R20
EXB-38V472JV
5
4
SD_CD
SD_WP
①　変更
NC
GND
CD_SW
CD_WP_COMMON
WP
10
11
12
SSP0_MISO
CPU_JRTCK
CPU_JTDO
13
14
SSP0_SCLK
DAT2
CD/DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
UART0_RXD
UART0_TXD
REGIN
RST
SUSPEND
SUSPEND Vdd
RI
C
8
7
6
5
10uF
10uF
C29
SSP0_MSS
SSP0_MOSI
10uF
C28
9
1
2
3
4
5
6
7
8
C37 0.1uF
NC3
NC4
NC5
NC6
NC11
CPU_JTMS
CPU_JTCK
3
4
5
6
26
C34
R19
22uF
C33
1uF
10uF
PON
SW
C35 0.015uF
2
1.5K
1
P1
DM1AA-SF-PEJ
CPU_JTDI
+3.3
C32
SW1
内層プレーン
14
13
12
11
10
9
8
36
25
16
39
38
15
7
40
20
19
10uF
⑫　スライド・スイッチ
に変更（IS-1250）
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VSENSE
NC10
NC9
EAOUT
EAIN
NC8
NC7
COMP
PGND4
PGND3
C30
内層プレーン
SD Card SLOT
9
12
11
2
C27 0.1uF
+3.3
44
43
42
31
30
3
2
NC16
NC15
NC14
NC13
NC12
+5V
1
EN5535QI
J3
DCJACK
U8
EN5335
1 NC1
21 PVIN1
22 PVIN2
23 PVIN3
24 PVIN4
28 AVIN
27 ROCP
35 POK
37 SS
41 ENABLE
32 VS2
33 VS1
34 VS0
2 NC2
29 AGND
17 PGND1
18 PGND2
C31
＋５Ｖは太く
nRESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CPU_nJTRST
CP2102
CP2102
1
2
+5V
U7
J2
R18
EXB-38V103JV
3
4
+3.3
+3.3
J6
USB_DN
USB_DP
R21
R22
R23
1.5K
27
27
1
2
3
4
5
CU0416SD
USB Mini-B
Connector
UART1_TXD
UART1_RXD
EXT_CONN0
EXT_CONN1
EXT_CONN2
EXT_CONN3
EXT_CONN4
EXT_CONN5
EXT_CONN6
EXT_CONN7
FPGA_IN6
FPGA_IN7
FPGA_IN8
FPGA_IN9
FPGA_IN10
FPGA_IN11
FPGA_IN12
FPGA_IN13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
CON20
VIN1
VOUT3
VIN2
VOUT2
ENABLE VOUT1
NC1
VSENSE
NC2
NC7
NC3
NC6
VS2
NC5
VS1
NC4
VS0
VFB
GND1
GND2
+3.3
7内層プレーン
6
5
15
14
13
12
11
16
C
1
2
20
8
9
10
17
18
19
3
4
10uF
GND
C40 4.7uF
内層プレーン
10uF
VIN1
VOUT3
VIN2
VOUT2
ENABLE VOUT1
NC1
VSENSE
NC2
NC7
NC3
NC6
VS2
NC5
VS1
NC4
VS0
VFB
GND1
GND2
U11 EN5311QI
7
6
5
15
14
13
12
11
16
C42
1
2
20
8
9
10
17
18
19
3
4
EN5311QI
C39 4.7uF
10uF
内層プレーン
EN5311QI
U10 EN5311QI
7
6
5
15
14
13
12
11
16
C41
VIN1
VOUT3
VIN2
VOUT2
ENABLE VOUT1
NC1
VSENSE
NC2
NC7
NC3
NC6
VS2
NC5
VS1
NC4
VS0
VFB
GND1
GND2
EN5311QI
C38 4.7uF
U9 EN5311QI
1
2
20
8
9
10
17
18
19
3
4
+1.2
External
Connector
+5V
+1.8
J5
+5V
+2.5
C43
+5V
A
Title
CQ_IMGP
Size
A2
Date:
5
4
3
2
Document Number
<Doc>
Rev
0.1
Sunday, April 12, 2009
1
Sheet
1
of
2