ソフトバンクが買収したARMの最新技術動向

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ソフトバンクが買収したARMの最新技術動向

企業分析イノベーションレポート
No.R161220102
ARM
分析対象特許情報：米国（ＵＳ）
2016年12月20日発行
イノベーションリサーチ株式会社
Copyright 2016 Innovation Research Corporation
1
本レポートとは
他社の研究開発動向を簡易的に探ることができるエンジニア向けの研究開発動向調査レポートです。
主に、特許情報を利用して執筆されています。
◇こんな方に使ってほしい
◇作成工程
研究開発を行っていて、日々気になる事―
それは、技術動向、競合企業動向ではないでしょうか。特許情報
を紐解けば、比較的正確にそれを掴む事が可能です。
しかし、特許情報分析には、検索式の作成や企業名のゆらぎの
処理等が必須であり、分析結果の解釈等に、一定の難しさがあ
ることも確かです。
また、このような分析は、社内の知的財産部門等で行うことも可
能ですが、全ての分野、全ての企業の分析を行う事は非常に手
間がかかります。特に新規事業などのこれから事業化していく分
野については、社内リソース的に十分に知財分析をすることが
難しいと考えられます。
そこで、我々は、社内リソースとして十分に調べることが出来て
いない分野・企業の動向調査レポートをご提供し、エンジニアの
皆様のお悩みを少しでも解消させて頂ければと考えております。
技術把握
検索式
作成
対象企業
• 技術内容を理解し、技術トレンドを把握します。
• 特許情報を収集するにあたり、できるだけ漏れ、ズレのない検索式
を作成します。
• 主要プレイヤーを10社程度抽出します。
抽出
• 特許DB上の名称ゆらぎ、社名変遷、企業買収、事業買収等の情報を
出願人
踏まえて分析を行います。（※子会社、関連会社については、親会
名寄せ
社のグループとして分析している場合があります。）
皆様の研究開発が実り多きものとなることを願っております。
• 次頁以降掲載のコンテンツ作成に必要な分析処理を行います。
分析
Copyright 2016 Innovation Research Corporation
2
－企業分析イノベーションレポート－
1
対象企業について
1-1 この１枚でわかる！サマリー
1-2 出願状況がわかる！
1-3 現在保有する重要特許の権利満了時期は？
1-4 グローバル戦略がわかる！～外国出願～
1-5 パートナー戦略がわかる！～共同出願～
1-6 キーパーソン発明者がわかる！
1-7 注力している技術内容がわかる！
（別紙）
□ 技術内容ごとの解決手段がわかる！～イノベーション・チャートTM～
□ 重要出願リスト（外国出願あり（各国）/共同出願）
□ 注目度の高い特許出願リスト（被引用回数TOP10）
Copyright 2016 Innovation Research Corporation
3
1．対象企業について
Copyright 2016 Innovation Research Corporation
4
1-1 この1枚でわかる！サマリー
①ステータス
ステータス
ARM
②重要出願
件数
区分
登録記録あり
1,121
登録記録なし
0
③外国出願
0
件数
外国出願あり（各国）
1,000
④共同出願
2,000
Ｎｏ．
英国
1,119
中国
共同出願人
件数
1
GRISENTHWAITE RICHARD
ROY
19
2
NYSTAD JORN
17
3
UNIVERSITY OF MICHIGAN
17
4
THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
17
5
HORLEY JOHN MICHAEL
17
日本
合計（総出願件数）
1,121
欧州
台湾
2008年以前
（上記では、無効審判請求あり以外は出願人の
判断で放棄したと考えられるものを除外して算出
している。また、本レポートでは、上記の他共同
出願を重要出願として分析している。）
⑩
⑨
⑧
⑥⑦
⑤
④
③
2014
2012
2010
2008
2006
2004
2002
2000
②
1996
出願年
（共同出願人が多い場合、特許出願件数上位を抽出）
⑦技術内容構成比
180
160
140
120
100
80
60
40
20
0
1998
140
120
100
80
60
40
20
0
（出願国が多い場合、特許出願件数上位を抽出）
⑥発明者数推移
発明者数
出願件数
⑤出願件数推移
2009年以降
出願年
①
②
③
④
⑤
⑥
⑦
⑧
⑨
⑩
①
②
③
④
⑤
⑥
⑦
⑧
⑨
⑩
対象企業
①
電気的デジタルデータ処理
静的記憶
電気的変量の測定；磁気的変量の測定
パルス技術
イメージデータ処理または発生一般
デジタル情報の伝送，例．電信通信
静的手段を用いて可変情報を表示する表示装置の制御
半導体装置
符号化，復号化または符号変換一般
画像通信，例．テレビジョン
（各特許出願に付与されている特許分類を基に作成）
Copyright 2016 Innovation Research Corporation
5
（各特許出願に付与されている特許分類を基に作成）
1-2 出願状況がわかる！
ARM
出願状況及び件数推移は、以下のとおりである。
◇ステータス
件数
140
登録記録あり
1,121
登録記録なし
0
合計（総出願件数）
120
0%
100
出願件数
ステータス
◇出願件数推移
1,121
100%
80
60
40
20
0
登録記録あり
登録記録なし
出願年
ステータスについて
●「出願・審査・審判中」は、今後権利となりうるカテゴリである。 ●「不登録確定」は、出願をしたが、何らかの理由で権利とならなかったカテゴリである。 ●「権利存続中」は、現在保
有している特許であり、権利行使可能なカテゴリである。特許ライフは、原則最長20年であり、いずれ全権利が消滅する。 ●「権利消滅」は、かつて権利であったが、期間満了や放棄
等により権利を失ったカテゴリである。
出願件数推移について
●出願件数推移は、現在の、当技術のライフサイクル把握に有用である。
Copyright 2016 Innovation Research Corporation
6
1-3 現在保有する重要特許の権利満了時期は？
ARM
重要出願、保有する重要特許の残存は以下のとおりである。
◇重要出願
◇現在保有する重要特許の残存件数
1,200
区分
件数
1,000
1,119
残存権利数
外国出願あり（各国）
800
600
400
200
0
各年末時点
重要出願について
●「外国出願あり」「拒絶査定不服審判あり」「分割出願」「早期審査」いずれも、シンプルな国内出願に比べ投資額がかさむことから、これらの出願は、出願人が重要視しているもので
ある考えられる。 ●ここでいう外国出願とは、本分析対象の日本出願に関連した外国ファミリー出願を指す。本レポートでは、各ファミリーにおける国数ではなく、各ファミリーにおける
各国への全出願件数をカウントしている。ただし、本レポートの分析対象国に出願しないものもあることから、必ずしも全ての外国出願がカウントされているわけではない。なお、重複カ
ウントとなる可能性が高いPCT出願、EPC出願等自体はカウントしていない。 ●「異議申立あり」「無効審判請求あり」は、他者により、邪魔な特許だとして、異議申立、無効審判請求
がなされたものである。 ●「異議申立あり」「無効審判請求あり」以外は、出願人自らの判断で放棄したと考えられるものを除外してカウントしている。
重要特許の残存件数について
●特許権のライフは、維持し続けた場合、最長20年である。現在有効な重要特許を、全て満了まで維持し続けた場合、いつごろどの程度の件数となるかを把握する。 ●将来取得す
る権利は捨象している。 ●当技術における重要特許が、いつごろ切れるのかを俯瞰することができる。 ●重要特許とは、上記重要出願群及び共同出願となっているもののうち、権
利存続中のものをいう。
Copyright 2016 Innovation Research Corporation
7
1-4 グローバル戦略がわかる！～外国出願～
ARM
外国出願先は、以下のとおりである。
◇出願先国別ランキング
0
500
出願件数
1,000
1,500
2,000
英国
中国
日本
欧州
2008年以前
台湾
2009年以降
ドイツ
イスラエル
オーストラリア
韓国
マレーシア
外国出願について
●ここでいう外国出願とは、本分析対象の日本出願に関連した外国ファミリー出願を指す。本レポートでは、各ファミリーにおける国数ではなく、各ファミリーにおける各国への全出願
件数をカウントしている。ただし、本レポートの分析対象国に出願しないものもあることから、必ずしも全ての外国出願がカウントされているわけではない。●市場となりうる国、生産拠
点となる国等を把握することが可能である。 ●「欧州」とは、ヨーロッパ特許条約（EPC）に基づいてされる出願を指す。ヨーロッパ各国への出願には、①EPC出願（特許を付与するか
否かの審査を伴う）後、各国移行手続きする方法と、②直接国ごとに出願する方法がある。
Copyright 2016 Innovation Research Corporation
8
1-5 パートナー戦略がわかる！～共同出願～
ARM
以下の企業との共同出願が認められ、パートナーシップが推認される。
◇共同出願人ランキング
Ｎｏ．共同出願人
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
出願件数
GRISENTHWAITE RICHARD ROY
NYSTAD JORN
UNIVERSITY OF MICHIGAN
THE REGENTS OF THE UNIVERSITY OF MICHIGAN
HORLEY JOHN MICHAEL
ARM NORWAY AS
CRASKE SIMON JOHN
WILLIAMS MICHAEL JOHN
BULL DAVID MICHAEL
FLYNN DAVID WALTER
ROSE ANDREW CHRISTOPHER
IDGUNJI SACHIN SATISH
PENTON ANTONY JOHN
DAS SHIDHARTHA
LUTZ DAVID RAYMOND
HUGOSSON OLA
NYSTAD JøRN
RIOCREUX PETER ANDREW
MYERS JAMES EDWARD
PERSSON ERIK
19
17
17
17
17
13
13
13
12
11
10
10
8
8
8
8
8
7
7
7
共同出願について
●共同出願の状況を確認することで、競合のパートナー戦略を読み解くことができる。
Copyright 2016 Innovation Research Corporation
9
1-6 キーパーソン発明者がわかる！
ARM
発明者数推移と発明者別出願件数を以下に示す。
◇発明者別出願件数ランキング
◇発明者数推移
<全期間>
10
0
2
20
30
出願件数
40
50
60
70
80
Grisenthwaite, Richard Roy
Biles, Stuart David
Bull, David Michael
Rose, Andrew Christopher
Flynn, David Walter
Flautner, Krisztian
Symes, Dominic Hugo
Seal, David James
Horley, John Michael
Craske, Simon John
180
160
140
120
発明者数
0
100
80
<直近5年>
60
40
20
2014
2013
2012
2011
2010
2009
2008
2007
2006
2005
2004
2003
2002
2001
2000
1999
1998
1997
1996
0
出願年
4
6
出願件数
8
10
12
14
16
18
Nystad, Jorn
Grisenthwaite, Richard Roy
Tune, Andrew David
Chong, Yew Keong
Yeung, Gus
Scalabrino, Luca
Burgess, Neil
Lutz, David Raymond
Hold, Betina
Kumar, Nidhir
発明者数推移について
●発明者数の推移を見ることで、各社の開発予算感を推測することが可能である。
発明者別出願件数
●歴代の功労者が確認でき、特に近年の出願に携わっている上位発明者が注目される。
Copyright 2016 Innovation Research Corporation
10
1-7 注力している技術内容がわかる！
ARM
技術内容の全体構成比および年別構成比推移を示す。
◇技術内容構成比/同推移
（参考情報）
100%
⑩
80%
⑤
④
③
②
⑨
⑧⑨⑩
⑥⑦
⑧
60%
⑦
対象企業
⑥
40%
①
⑤
20%
④
③
0%
2009
2010
2011
2012
出願年
2013
2014
②
①
⑩ 画像通信，例．テレビジョン
⑨ 符号化，復号化または符号変換一般
⑧ 半導体装置
⑦
静的手段を用いて可変情報を表示する表示装置の制
御
⑥ デジタル情報の伝送，例．電信通信
⑤ イメージデータ処理または発生一般
④ パルス技術
③ 電気的変量の測定；磁気的変量の測定
② 静的記憶
① 電気的デジタルデータ処理
（各特許出願に付与されている特許分類を基に作成）
技術内容構成比/同推移について
●トレンド技術を知る。 ●直近期は、必ずしも全てが公開されているわけではないため、参考情報となる。
●複数の技術に係る出願については、それぞれの技術において１件とカウントして集計している。 ●「その他」には、最新技術のため、分類できないものを含む場合がある。
Copyright 2016 Innovation Research Corporation
11
■お問合せ先■
イノベーションリサーチ株式会社
住所：〒115-0045
東京都北区赤羽1-59-9 ネスト赤羽1F
電話：03-6903-8489
URL：http://www.innovation-r.com/
（担当：武藤）
本レポートの著作権は、イノベーションリサーチ株式会社に帰属します。
Copyright 2016 Innovation Research Corporation
12
（別紙）
□ 技術内容ごとの解決手段がわかる！～イノベーション・チャートTM～
□ 重要出願リスト（外国出願あり（各国）/共同出願）
□ 注目度の高い特許出願リスト（被引用回数TOP10）
あ
Copyright 2016 Innovation Research Corporation
13
技術内容ごとの解決手段がわかる！～イノベーション・チャートTM ～
技術別の、手段に関するキーワードとそれに対応する重要出願番号
技術内容
キーワード
重要出願番号
US9454633B2
US9430419B2
US9383999B2
US9361112B2
US9286196B1
US9280675B2
US9218285B2
US9176737B2
US9146901B2
US9116711B2
data processing circuitry memory instruction one be at value access
US9104425B2
apparatus least cache logic first plurality signal processor
US9075622B2
instructions A provided control within operation second unit circuit
US9032252B2
request program storage address values operable register associated
US9009450B2
system device output mode input trace store such stored set state
US8954715B2
電気的デジタルデータ execution method transaction clock predetermined result corresponding
US8966494B2
①
処理
secure operations requests between interrupt can registers level
US8898430B2
comprising elements error domain response power number responsive write US8892923B2
configured operating generate information priority perform controller
US8819309B1
bus storing portion 2 generated signals arranged interface whether read US8788887B2
performing performed stream exception element pipeline sequence nonUS8719555B2
secure integrated multiple order buffer line
US8707106B2
US8661225B2
US8607006B2
US8589927B2
US8549199B2
US8478947B2
US8448251B2
US8458532B2
US8397193B2
US8352794B2
US8321861B2
US9449717B2
US9142266B2
memory data circuitry signal voltage access at line bit first control
US9042188B2
value one least cells read cell second plurality output circuit write
US8918700B2
level operation device associated lines storage be A processing provided
US8638622B2
error array address column supply power word input logic state node
US8386890B2
within such mode comprising stored clock configured signals between
US8230277B2
② 静的記憶
operable selected request cache strobe test arranged two apparatus
US8045402B2
portion predetermined path responsive response group method values
US7948816B2
storing integrated coupled controller units result provides addressed
US7805645B2
delay timing precharge generate reference latch transition assist
US7558104B2
switching columns row dependence An corresponding can region register
US7324368B2
enable store record operations pulse sequence
US7185159B2
US6366978B1
data circuit signal circuitry processing at test one integrated
functional scan value diagnostic output least be first plurality input
voltage clock error operable memory provided chain serial within latch US9404966B2
circuits control controller second apparatus delay associated time units US8555124B2
mode An communication operation debug logic interface A operating block US8145958B2
電気的変量の測定；磁
③
2 path comprising such bus predetermined testing register between
US7770078B2
気的変量の測定
provides device storage can unit signals digital 6 parameter 4 wrapper US7444271B2
power ring reference configuration instruction transaction response
US7293212B2
values access 18 configured stage domain sequence portion via master it US6708317B2
internal self-test provide detection supply generated perform captured
controlling system non-delayed generating performance method
US9454451B2
US9430381B2
US9378113B2
US9361111B2
US9286222B2
US9256466B2
US9213828B2
US9201816B2
US9170979B2
US9122890B2
US9087017B2
US9075621B2
US9059726B2
US9015719B2
US8966282B2
US8966323B2
US8922572B2
US8892801B2
US8819378B2
US8775824B2
US8719553B2
US8713375B2
US8650470B2
US8621242B2
US8583897B2
US8548962B2
US8479033B2
US8443170B2
US8451026B2
US8386754B2
US8347131B2
US8307138B2
US9407265B2
US9171594B2
US9036427B2
US8885429B1
US8611172B2
US8355293B2
US8228745B2
US8045401B2
US7940546B2
US7729185B2
US7533226B2
US7308623B2
US7068545B1
US6172530B1
US9454397B2 US9454313B2 US9449717B2 US9448875B2
US9424045B2 US9417877B2 US9405939B2 US9411362B2
US9355014B2 US9378186B2 US9378175B2 US9378162B2
US9355061B2 US9348688B2 US9348598B2 US9330035B2
US9304926B2 US9304923B2 US9299126B2 US9300716B2
US9268942B2 US9269418B2 US9262123B2 US9256732B2
US9229908B2 US9223701B2 US9223677B2 US9213650B2
US9201651B2 US9176856B2 US9202071B2 US9189881B2
US9164842B2 US9170819B2 US9146870B2 US9164910B2
US9104400B2 US9104479B2 US9122613B2 US9128531B2
US9092215B2 US9081564B2 US9092345B2 US9070200B2
US9042188B2 US9052909B2 US9021233B2 US9037835B1
US9058179B2 US9047184B2 US9021298B2 US9009208B2
US9015424B2 US9003123B2 US8995191B2 US8990518B2
US8965945B2 US8966309B2 US8935592B2 US8959318B2
US8966228B2 US8965946B2 US8959304B2 US8949547B2
US8924615B2 US8892623B2 US8930601B2 US8924766B2
US8856408B2 US8874975B2 US8874883B2 US8881078B2
US8803898B2 US8812997B2 US8838929B2 US8826097B2
US8762744B2 US8769251B2 US8769307B2 US8799621B2
US8725953B2 US8756377B2 US8751833B2 US8738971B2
US8706936B2 US8706965B2 US8677104B2 US8713292B2
US8656078B2 US8667199B2 US8661232B2 US8639987B2
US8621272B2 US8621336B2 US8615687B2 US8601167B2
US8578136B2 US8595280B2 US8572329B2 US8601485B2
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USRE43248E1
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US9436473B2
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US8732499B2
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US8463960B2
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US8356119B2
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US9171634B2
US9064559B2
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US8103922B2
US7961490B2
US7855924B2
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US7339842B1
US7248508B1
US6552949B1
US9170282B2
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US8036854B2
US7743294B2
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US7269766B2
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US8433961B2
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US7734974B2
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US7206982B1
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US8330478B2
US7913131B2
US7627462B2
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US7124274B2
US8779787B2
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US7856346B2
US7574314B2
US7330798B2
US7085978B2
US8619554B2
US8185791B2
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US7308631B2
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US8615687B2
US8112681B2
US7809972B2
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US6779143B2
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US8407540B2
US7949914B2
US7701240B2
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イノベーション・チャートTMについて
●各技術内容において、どんな手段で解決しようとしているかを把握し、技術開発動向を知る。●手段キーワードとは、特許要約書の【解決手
段】に記載された各単語のことを指す。（「イノベーション・チャート」は、イノベーションリサーチ㈱のトレードマークです。）
Copyright 2016 Innovation Research Corporation
US9021298B2
US8407025B2
US7898278B2
US7650551B2
US7389459B2
US7197680B2
US8862935B2
US8352815B2
US7893722B2
US7603605B2
US7363176B2
US7142996B2
技術内容ごとの解決手段がわかる！～イノベーション・チャートTM ～
技術別の、手段に関するキーワードとそれに対応する重要出願番号
技術内容
④ パルス技術
⑤
イメージデータ処理ま
たは発生一般
デジタル情報の伝送，
⑥
例．電信通信
静的手段を用いて可変
⑦ 情報を表示する表示装
置の制御
⑧ 半導体装置
キーワード
signal voltage data circuit clock value circuitry power input output
mode level retention device latch first one at second control switching
path storage transistor be least provided operable high low sleep
plurality rail processing A logic supply integrated such transition
operation source comprising current response trace within between stage
virtual state devices 14 signals An normal gating elements bus 2
configured forward gate portion circuits two provides powered receive
difference scan speed 16 predetermined arranged slave change controlled
intermediate flip-flop operational responsive 12 leakage feedback via
tuning higher ring block node generating oscillator tristateable domain
driver it pulse can clocked
data processing texture graphics be values block rendering memory tile
fragment value set shader depth pipeline circuitry system stored output
A generated frame curve buffer unit primitive at operation one pixel
elements blocks encoded input display it image generate within plurality
cache processor stroked operations program sampling 4 least can provided
use space individual two fragments determined indicating tiles
corresponding processed thread function compression received 3 up 1
color renderer accumulated primitives texels whether rendered 2
different occlusion local hardware points order information other 5 12
point path execution associated comparison array position portion
buffers colors state vertex mode determine
data processing secure processor mode non-secure domain logic device
one apparatus plurality storage access memory at operable least unit be
first buffer trace signal second control clock slave within provided
master program operating circuitry between circuit packets transfer
elements method A interface core comprising system value bus test
multiple operation engine request exception instruction communication
stream predetermined dependence invention such configuration values file
associated transfers table input transaction storing output accessible
monitor receiving corresponding present modes element FIFO provides
signals stored generate main single network priority coupling sequence
shared store can executing whether number via arbitration initiator
order switching controller
data texture values be graphics processing block memory pixel frame
tile value set output generated surface pipeline system buffer region
stored within encoded blocks A circuitry colors rendering compression
operation fragment elements tiles can table 2 it display color one new
local occlusion generate regions curve primitive second shader two at
program pixels base processed order corresponding 6 surfaces plurality
determined video input encoding 1 processor 80 respective comparison
texels threshold individual first written performance level 4 provided 3
whether logic palette indicating rendered error position image
parameters main method alpha Table coded render font version positions
representing In read
circuit cell be provided gate standard voltage diffusion first
diagnostic between one second elements signal layers integrated
functional circuitry region layer connection core A cells plurality
electrode associated at routing scan within power transaction data
interface method row operation least two component connected 18 chain
storage such 4 layout formed providing An supply can gated test model
processing input 20 area reset value bit 16 components 36 level line
circuits static type conductivity source substrate path via opening
memory grid apparatus protection 12 columns required conductor both
block controller blocks forming 34 28 regions steps vias over speed 38
bypass
重要出願番号
US9450571B2
US8941428B2
US8427214B2
US8154353B2
US7325168B2
US6779143B2
US9432009B2
US8922247B2
US8421513B2
US8067971B2
US7262631B2
US6278334B1
US9407265B2
US8742827B2
US8456199B2
US7924056B2
US7221205B2
US6218879B1
US9391614B2 US9379710B2 US9374072B2
US8717084B1 US8717078B2 US8519775B2
US8456223B2 US8427198B1 US8456214B2
US7893722B2 US7830176B2 US7737720B2
US7180348B2 US7154317B2 US7149933B2
US6043698A US6034545A US5918042A
US9306545B2
US8493120B2
US8451039B2
US7616041B2
US7117277B2
US9170282B2
US8497702B2
US8407540B2
US7617409B2
US7005910B2
US9110643B2
US8502561B2
US8390328B2
US7514975B2
US7005913B2
US8957703B2
US8421501B1
US8319518B2
US7310755B2
US7005889B2
US9454844B2
US9286714B2
US9070200B2
US8928667B2
US8477148B2
US7920139B2
US9430381B2
US9256975B2
US9041723B2
US8891886B2
US8421821B2
US7426320B2
US9406155B2
US9218793B2
US9058637B2
US8803898B2
US8339409B2
US6259459B1
US9367953B2
US9214006B2
US8976177B2
US8766991B2
US8345051B2
US9349210B2
US9177415B2
US9014496B2
US8717366B2
US8289343B2
US9349209B2
US9189881B2
US8988443B2
US8743135B2
US8199146B2
US9349156B2
US9153070B2
US8978038B2
US8698828B2
US8159491B2
US9317948B2
US9142037B2
US8922568B2
US8681168B2
US8102402B2
US9324163B2
US9122646B2
US8922572B2
US8698820B2
US8106921B2
US9299126B2
US9092345B2
US8928668B2
US8675006B2
US8059144B2
US9405939B2
US8347131B2
US7661104B2
US7370210B2
US7134117B2
US9300716B2
US8171311B2
US7661105B2
US7305712B2
US7085874B2
US9294301B2
US8161367B2
US7630388B2
US7315600B2
US7031337B2
US9292036B2
US8082589B2
US7627807B2
US7290075B2
US7016370B2
US9288258B2
US8045573B2
US7509502B2
US7219179B2
US7003699B2
US9280675B2
US7949866B2
US7508836B2
US7269759B2
US6876941B2
US9226127B2
US7924858B2
US7549059B2
US7240268B2
US9104400B2
US7886098B2
US7489752B2
US7181556B2
US8966282B2
US7920584B2
US7487367B2
US7197671B2
US8630358B2
US7849310B2
US7383587B2
US7143221B2
US9430381B2
US9041723B2
US8421821B2
US6304198B1
US9406155B2
US8988443B2
US8339409B2
US6236342B1
US9349210B2 US9349156B2 US9218793B2 US9177415B2 US9189881B2 US9195426B2 US9182934B2 US9070200B2
US8922572B2 US8831341B2 US8803898B2 US8766991B2 US8743135B2 US8698828B2 US8681168B2 US8477148B2
US8339414B2 US8289343B2 US8102402B2 US8144167B2 US8115783B2 US8106921B2 US8059144B2 US8044971B2
US6069611A
US9454633B2 US8873209B2 US8648654B1 US8451026B2 US8024690B2 US7960759B2 US7863733B2 US7745275B2 US7706172B2 US7366650B2
US7228457B2 US7069376B2 US7002258B2 US6779143B2 US6708317B2
イノベーション・チャートTMについて
●各技術内容において、どんな手段で解決しようとしているかを把握し、技術開発動向を知る。●手段キーワードとは、特許要約書の【解決手
段】に記載された各単語のことを指す。（「イノベーション・チャート」は、イノベーションリサーチ㈱のトレードマークです。）
Copyright 2016 Innovation Research Corporation
技術内容ごとの解決手段がわかる！～イノベーション・チャートTM ～
技術別の、手段に関するキーワードとそれに対応する重要出願番号
技術内容
キーワード
重要出願番号
data value processing error circuitry values within signal apparatus be
code control table bit number device stored second operation first A
plurality arranged memory group one provided digital symbols stream unit
symbol least instruction two generate bits operations new select list at
2 state floating-point can store blocks cache operable frequency
US9384091B2 US9059726B2 US9047184B2 US8826097B2 US8694862B2 US8640008B2 US8473819B2 US8423752B2 US8378861B2 US8374098B2
符号化，復号化または
⑨
generator associated codes fixed-point conversion corrupted between
US8352819B2 US8145960B2 US7945607B2 US7934029B2 US7936290B2 US7328391B2 US7269759B2 US7236995B2 US7145480B2 US6958718B2
符号変換一般
perform storage representation compression 6 comprising generated
US6831952B2 US6504495B1 US6411958B1 US6304198B1 US6236342B1
configured detection responsive elements ordering lane size pixel font
Table process coded reference corresponding Error retention method
selector registers scores such errors predetermined timing circuits
instructions selected parallel 8 N index lookup input via stabilisation
data values processing video texture circuitry set input at block one
least generate frame elements encoded first output be processor stage
encoding plurality apparatus signal image filter second method luminance
base indicating color stored internal secure configured reference
logical value A sample computation between fragment M representing
画像通信，例．テレビ portion transform pipeline pixel domain rendering array node filtered N US9407931B2 US9378186B2 US9177415B2 US9142037B2 US9041723B2 US9058637B2 US9014496B2 US8831341B2 US8773593B2 US8594177B2
⑩
ジョン
use frames operations mode control required colors blocks stream down- US8532192B2 US8421821B2 US8332660B2 US8106921B2 US8082589B2 US7426320B2 US7315875B2 US6895056B2
sampled provided performance space comparison operation filtering
parameter non-secure item perform determined current other performing
comprising compare generated buffer sets derived performs function sum
decoding pixels indicator 30 predetermined two term portions quadtree
compressed
イノベーション・チャートTMについて
●各技術内容において、どんな手段で解決しようとしているかを把握し、技術開発動向を知る。●手段キーワードとは、特許要約書の【解決手
段】に記載された各単語のことを指す。（「イノベーション・チャート」は、イノベーションリサーチ㈱のトレードマークです。）
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
1
US9454844B2
2014/10/2 Early depth testing in graphics processing
2
US9454633B2
ARM
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
US9454397B2
2014/6/18 Via placement within an integrated circuit
ARM
Apparatus and method for performing data scrubbing on a
2013/2/11
ARM
memory device
2015/4/9 Data processing systems
ARM
3
US9454451B2
4
5
登録記録あり
0
○
US9454313B2
2014/6/10 Dynamic selection of memory management algorithm
ARM
登録記録あり
0
○
6
US9450571B2
2014/6/3 Data and clock signal voltages within an integrated circuit ARM
登録記録あり
0
○
7
US9449717B2
2014/6/20 Memory built-in self-test for a data processing apparatus ARM
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM;JONES SIMON;TAPPLY JOE
登録記録あり
DOMINIC MICHAEL
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM;FORD SIMON
ANDREW;STYLES CHRISTOPHER 登録記録あり
JAMES
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
8
US9448875B2
2013/12/6 Error recovery within integrated circuit
9
US9419551B2
10
US9442878B2
11
US9442856B2
12
US9436473B2
13
US9432009B2
14
US9430421B2
15
US9430419B2
16
US9430381B2
17
US9424045B2
18
US9417877B2
19
US9405939B2
2008/10/7 Data processing on a non-volatile mass storage device
20
US9411362B2
2014/2/28
21
US9411774B2
22
US9411662B2
2014/9/17 Motor driver and a method of operating thereof
Parallel snoop and hazard checking with interconnect
2014/4/17
circuitry
Data processing apparatus and method for handling
2015/6/5
performance of a cache maintenance operation
Scheduling program instructions with a runner-up
2013/10/8
execution position
2013/11/15 Circuit delay monitoring apparatus and method
2014/3/12 Interrupt signal arbitration
Synchronizing exception control in a multiprocessor
2011/10/13 system using processing unit exception states and group
exception states
Processing order with integer inputs and floating point
2014/4/21
inputs
Data processing apparatus and method for controlling
2013/1/29 use of an issue queue to represent an instruction
suitable for execution by a wide operand execution unit
Switching between dedicated function hardware and use
2014/6/9
of a software routine to generate result data
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM
Storage circuitry and method for propagating data values
ARM
across a clock boundary
2013/4/23 Memory access control
ARM
Controlling priority levels of pending threads awaiting
2013/7/16
ARM
processing
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
23
公報番号
US9407931B2
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;ANDERSSON PATRIK;EDSö
登録記録あり
TOMAS
2010/6/25 Motion vector estimator
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
2
○
ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD 登録記録あり
ROY;CRASKE SIMON JOHN
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
登録記録あり
0
○
Integrated circuit with signal assist circuitry and method
2013/11/25
ARM
of operating the circuit
ARM;OTERHALS JON
ERIK;CROXFORD
2010/9/24 Graphics processing systems
DAREN;ERICSSON
LARS;NYSTAD JøRN;LILAND
EIVIND
Performance characteristic monitoring circuit and
ARM;DWIVEDI SANDEEP;HOLD
2012/7/13
method
BETINA
2013/3/20 Technique for freeing renamed registers
ARM
Clock state control for power saving in an integrated
2014/7/29
ARM
circuit
Error code management in systems permitting partial
2014/5/21
ARM
writes
ARM;SEAL DAVID
2012/11/21 Conditional compare instruction
JAMES;CRASKE SIMON JOHN
2013/12/12 Tracing of a data processing apparatus
ARM
ARM;NYSTAD JøRN;LJOSLAND
2009/6/3 Graphics processing systems
BORGAR;SøRGåRD EDVARD
24
US9407265B2
25
US9406155B2
26
US9404966B2
27
US9400655B2
28
US9391614B2
29
US9384091B2
30
US9383999B2
31
US9378113B2
32
US9367953B2
33
US9355014B2
2011/8/10
34
US9379710B2
35
US9378186B2
2014/2/27 Level conversion circuit and method
Data processing apparatus and method for performing a
2014/3/26 transform between spatial and frequency domains when
processing video data
36
US9378175B2
2007/11/1 Data transfer between a master and slave
37
US9378162B2
2013/5/21 Handling and routing interrupts to virtual processors
38
US9374072B2
39
US9372811B2
Debug instruction set allocation according to processor
operating state
2014/5/2 Post fabrication tuning of an integrated circuit
2012/12/13 Retention priority based cache replacement policy
ARM;CHAUSSADE
NICOLAS;BROYER PIERRE
MICHEL;LUC PHILLIPE
ARM
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No.
公報番号
出願日
タイトル (英語)
出願人
Data processing apparatus having first and second
2014/8/21 protocol domains, and method for the data processing
apparatus
40
US9372798B2
41
US9361236B2
42
US9361204B2
43
US9361112B2
44
US9361111B2
45
US9355061B2
46
US9349210B2
47
US9349209B2
48
US9349156B2
49
US9348688B2
50
US9348598B2
2013/4/23
51
US9324392B1
2014/10/23
52
US9330035B2
Memory device and method of performing a write
operation in a memory device
2013/5/23 Method and apparatus for interrupt handling
53
US9317948B2
54
US9324163B2
55
US9311244B2
56
US9323536B2
57
US9311088B2
58
US9311087B2
59
US9281027B1
60
US9286196B1
ARM;FLANDERS WILLIAM
HENRY;PRASADH
RAMAMOORTHY
GURU;TUMMALA ASHOK
KUMAR;JALAL
JAMSHED;MANNAVA
PHANINDRA KUMAR
ARM
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1
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ARM
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0
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ARM
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0
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ARM
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0
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ARM;MERRY BRUCE
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0
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2013/5/21 Adaptive frame buffer compression
ARM
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0
○
2014/2/20 Correlating trace data streams
ARM
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0
○
Data processing apparatus and method for pre-decoding
ARM
instructions to be executed by processing circuitry
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0
○
ARM
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2
○
ARM
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0
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2012/11/16 Method of and apparatus for processing graphics
ARM
登録記録あり
3
○
2013/5/30 Methods of and apparatus for compressing depth data
Enforcing ordering of snoop transactions in an
2014/8/25
interconnect for an integrated circuit
Identification of missing call and return instructions for
2013/5/2
management of a return address stack
Apparatus and method for mapping architectural registers
2013/6/26
to physical registers
Sticky bit update within a speculative execution
2012/12/21
processing environment
2014/10/10 Test techniques in memory devices
Program execution optimization using uniform variable
2015/1/8
identification
ARM
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ARM
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ARM
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ARM
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ARM
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0
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ARM
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0
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ARM
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0
○
2013/6/18 Handling write requests for a data array
Generating trace data including a lockup identifier
2013/2/19
indicating occurrence of a lockup state
2013/4/18 Return address prediction
Tracking speculative execution of instructions for a
2013/1/9
register renaming data store
Data processing apparatus and method for performing
2014/1/28
scan operations
Methods of and apparatus for using textures in graphics
2012/11/30
processing systems
2011/5/27 Graphics processing systems
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No.
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出願日
タイトル (英語)
出願人
Data processing apparatus and method for transferring
2013/4/30 workload between source and destination processing
ARM
circuitry
Master-slave flip-flop circuit and method of operating the
2014/1/14
ARM
master-slave flip-flop circuit
2013/7/23 Coherency control message flow
ARM
61
US9286222B2
62
US9306545B2
63
US9304926B2
64
US9304923B2
65
US9299126B2
66
US9300716B2
2013/3/12 Data coherency management
Image processing apparatus and a method of storing
2013/9/12 encoded data blocks generated by such an image
processing apparatus
2012/9/20 Modelling dependencies in data traffic
67
US9294301B2
2012/9/20
68
US9292298B2
69
US9292036B2
70
US9288258B2
71
US9286714B2
72
US9286069B2
73
US9280675B2
2012/2/27 Encrypting and storing confidential data
74
US9256466B2
75
US9268942B2
2013/6/7 Data processing systems
Providing a trustworthy indication of the current state of
2013/6/12
ARM
a multi-processor data processing apparatus
76
US9256975B2
77
US9269418B2
78
US9262123B2
Selecting between contending data packets to limit
latency differences between sources
Data processing apparatus having SIMD processing
circuitry
Data processing apparatus and method for
2013/5/24 communicating between a master device and an
asynchronous slave device via an interface
2013/7/8
2013/5/3
Communication using integrated circuit interconnect
circuitry
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1
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0
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ARM
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2
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ARM
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0
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ARM;TUNE ANDREW DAVID
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0
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ARM;TUNE ANDREW
DAVID;SALISBURY SEAN
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JAMES;BRUCE ALISTAIR CRONE
0
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ARM
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0
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ARM
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2
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ARM;MACE TIMOTHY
CHARLES;ROSE ANDREW
CHRISTOPHER
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0
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0
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1
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0
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0
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0
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ARM;HEGGELUND
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FRODE;GJERMUNDNES OYSTEIN
0
○
ARM;FELTON DONALD;ÖZER
EMRE;IDGUNJI SACHIN SATISH
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0
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ARM
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0
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2013/6/20 Apparatus and method for processing graphics primitives ARM
2012/12/21 Dynamic write port re-arbitration
2010/12/15 Graphics processing systems
Apparatus and method for controlling refreshing of data
in a DRAM
Data processing apparatus and method for performing a
2013/7/31
narrowing-and-rounding arithmetic operation
2012/2/6
審査･権利状況被引用回数外国出願
ARM
ARM;BRELOT JEANBAPTISTE;AIRAUD CEDRIC
DENIS ROBERT
ARM
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出願人
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Processing efficiency on secure systems having a host
processor and smart card
ARM;HARRIS PETER
WILLIAM;WILSON PETER
BRIAN;THORNTON TIMOTHY
CHARLES;MARTIN DAVID PAUL
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0
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ARM
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0
○
ARM
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ARM;SEAL DAVID
Apparatus and method for processing a bitfield
JAMES;GRISENTHWAITE
2011/9/22 manipulation instruction having a control value indicating
登録記録あり
RICHARD ROY;STEPHENS NIGEL
insertion or extraction form
JOHN
2013/12/13 Electric motor with plural stator components
ARM
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1
○
0
○
0
○
2013/6/25 Page table management
ARM
Receiver based communication permission token
2013/6/14
ARM
allocation
Variable mapping of memory accesses to regions within a
2012/11/26
ARM
memory
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0
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0
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0
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0
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0
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0
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2
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2
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0
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0
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0
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0
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79
US9256732B2
2007/11/1
80
US9251378B2
2014/3/20
81
US9208839B2
82
US9207937B2
83
US9214837B2
84
US9218302B2
85
US9213660B2
86
US9218285B2
87
US9213828B2
88
US9229908B2
89
US9226127B2
2011/9/29
90
US9223701B2
2013/4/12
91
US9223677B2
2008/6/11
92
US9218793B2
2012/10/24
93
US9214204B2
2014/3/19
94
US9214006B2
95
US9213650B2
Security protection of software libraries in a data
processing apparatus
2014/3/20 Predicting saturation in a shift operation
Data processing apparatus and method for protecting
2012/11/19 secure data and program code from non-secure access ARM
when switching between secure and less secure domains
2013/7/3 Identifier selection
2013/6/4
ARM
GIESECKE &
Method for provisioning of a network access for a mobile DEVRIENT;ARM;SPITZ
communication device using the mobile communication
STEPHAN;STERZINGER
device
HERMANN;BROWN ROBERT
JOHN
Data processing apparatus and method for performing
ARM
load-exclusive and store-exclusive operations
ARM;SWAINE ANDREW
BROOKFIELD;WILLIAMS
Generation of trace data in a multi-processor system
MICHAEL JOHN;HART DAVID
KEVIN;ROSE ANDREW
CHRISTOPHER
Intermediate value storage within a graphics processing
ARM
apparatus
Wordline pulse duration adaptation in a data storage
ARM
apparatus
Hidden surface removal in graphics processing systems ARM
2014/12/4 Memory management unit
ARM
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公報番号
96
US9213547B2
97
US9213359B2
98
US9189432B2
99
US9201749B2
100
US9176737B2
101
US9201816B2
102
US9201651B2
103
US9177415B2
104
US9176856B2
105
US9202071B2
106
US9189881B2
107
US9201656B2
108
US9195426B2
109
US9189646B2
110
US9182934B2
111
US9146901B2
112
US9170282B2
113
US9170979B2
出願日
タイトル (英語)
Processor and method for processing instructions using
2013/3/14
at least one processing pipeline
Interface for controlling the phase alignment of clock
2012/12/24
signals for a recipient device
2010/11/15 Apparatus and method for predicting target storage unit
2014/7/31 Diagnosing code using single step execution
Controlling the execution of adjacent instructions that
2011/2/7
are dependent upon a same data condition
Data processing apparatus and a method for setting
2013/8/14
priority levels for transactions
Data processing apparatus and method having integer
2010/5/3 state preservation function and floating point state
preservation function
Methods of and apparatus for encoding and decoding
2013/1/30
data
Data store and method of allocating data to the data
2013/7/8
store
Exception handling in a data processing apparatus having
2013/1/15
a secure domain and a less secure domain
2013/5/30 Graphics processing
Data processing apparatus and method for performing
2011/12/2 register renaming for certain data processing operations
without additional registers
Method and apparatus for generating an output surface
2014/4/17 from one or more input surfaces in data processing
systems
Protection circuity and method for controlling access by
2014/2/5
plural processes to a memory
Method and apparatus for generating an output surface
2013/9/20 from one or more input surfaces in data processing
systems
2011/8/26 Vector floating point argument reduction
2013/5/16 Controlling voltage generation and voltage comparison
Converging interconnect node controlling operation
related to associated future item in dependence upon
2012/3/23
data predicted based on current transaction data item
passing through
出願人
審査･権利状況被引用回数外国出願
ARM
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ARM
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ARM;REID ALASTAIR DAVID
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0
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ARM
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0
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ARM;CRASKE SIMON JOHN
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0
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ARM
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0
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ARM
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0
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ARM
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0
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ARM
ARM;BRELOT JEANBAPTISTE;AIRAUD CéDRIC
DENIS ROBERT
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0
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ARM
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0
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ARM
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0
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ARM
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0
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ARM;NYSTAD JORN
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0
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ARM
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0
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ARM;SALISBURY SEAN
JAMES;TUNE ANDREW DAVID
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0
○
ARM;TEYSSIER MELANIE
EMANUELLE LUCIE;BEGON
FLORENT;JAUBERT JOCELYN
FRANCOIS ORION;HUOT
NICOLAS JEAN PHILLIPPE
ARM
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No.
114
公報番号
US9164842B2
出願日
タイトル (英語)
2013/6/25 Error recovery within integrated circuit
Memory device and method of controlling leakage current
within such a memory device
Forwarding condition information from first processing
circuitry to second processing circuitry
Performance of accesses from multiple processors to a
same memory location
Memory circuitry using write assist voltage boost
出願人
審査･権利状況被引用回数外国出願
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
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ARM
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1
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ARM
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0
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ARM
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0
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ARM
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ARM;CHAUSSADE
NICOLAS;BROCHIER STEPHANE 登録記録あり
ERIC SEBASTIEN
0
○
0
○
115
US9171634B2
2013/3/14
116
US9170819B2
2013/1/9
117
US9146870B2
2013/7/24
118
US9142266B2
2013/11/19
119
US9164910B2
2008/2/21 Managing the storage of data in coherent data stores
120
US9158941B2
2006/3/16
Managing access to content in a data processing
apparatus
ARM;CROXFORD DAREN;FELTON
DONALD;KERSHAW
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DANIEL;WILSON PETER BRIAN
0
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121
US9171594B2
2012/7/19
Handling collisions between accesses in multiport
memories
ARM;DHOGALE VIVEK
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0
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0
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0
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ARM
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0
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ARM;NYSTAD JORN
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1
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ARM
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0
○
ARM
登録記録あり
1
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ARM
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0
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ARM
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0
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0
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0
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0
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122
US9158574B2
2011/11/18 Handling interrupts in data processing
123
US9153070B2
124
US9147451B2
125
US9142037B2
126
US9141338B2
127
US9116711B2
128
US9130433B2
129
US9122890B2
130
US9104400B2
2012/12/17 Hidden surface removal in graphics processing systems
Memory device and method of controlling leakage current
2013/3/20
within such a memory device
Methods of and apparatus for encoding and decoding
2013/7/2
data
2012/11/16 Storage circuit with random number generation mode
Exception handling in a data processing apparatus having
2012/11/19
a secure domain and a less secure domain
2013/11/14 Electronically controlled universal motor
Secure mechanism to switch between different domains
2013/9/6
of operation in a data processor
2014/12/30 Cryptographic support instructions
131
US9104479B2
132
US9105315B2
ARM;MANSELL DAVID
HENNAH;GLAUERT TIMOTHY
HOLROYD
ARM
ARM
ARM;LUTZ DAVID
Apparatus and method for rounding a floating-point value
2011/12/7
RAYMOND;BURGESS
to an integral floating-point value
NEIL;ROMERO SABRINA MARIE
ARM;HOLD
Controlling the voltage level on the word line to maintain BETINA;CHARAFEDDINE
2012/7/23
performance and reduce access disturbs
KENZA;LAPLANCHE YVES
THOMAS
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133
US9105327B2
2013/4/12
134
US9111596B2
135
US9122613B2
136
US9128531B2
137
US9122646B2
138
US9116844B2
2013/8/15 Memory access control in a memory device
ARM
Prefetching of data and instructions in a data processing
2013/3/7
ARM
apparatus
ARM;ELLIS SEAN
2012/2/22 Operand special case handling for multi-lane processing TRISTRAM;CHARLES SIMON
ALEX;BURDASS ANDREW
2012/9/20 Graphics processing systems
ARM
Data processing apparatus and method for analysing
2014/4/7 transient faults occurring within storage elements of the ARM
data processing apparatus
139
US9116790B2
140
US9110643B2
141
US9104425B2
2014/1/7 Apparatus and method for handling exception events
142
US9087017B2
2011/10/13 Controlling latency and power consumption in a memory
143
US9092215B2
144
US9081564B2
145
US9092345B2
146
US9070200B2
147
US9069652B2
148
US9098265B2
149
US9081685B2
150
US9081581B2
151
US9075622B2
出願日
2012/8/3
タイトル (英語)
出願人
Memory controller using a data strobe signal and method
ARM
of calibrating data strobe signal in a memory controller
Methods of and apparatus for storing data in memory in
data processing systems
2012/6/11 Leakage current reduction in an integrated circuit
Mapping between registers used by multiple instruction
sets
Converting scalar operation to specific type of vector
2012/4/4
operation using modifier instruction
2013/8/8 Data processing systems
2011/2/22
2013/5/2 Graphics processing systems
Integrated level shifting latch circuit and method of
2013/3/1
operation of such a latch circuit
Controlling an order for processing data elements during
2012/7/11
vector processing
Data processing apparatus and method for handling
2013/1/15
performance of a cache maintenance operation
2010/11/16 Size mis-match hazard detection
2008/1/23 Reducing errors in pre-decode caches
審査･権利状況被引用回数外国出願
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0
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0
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0
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登録記録あり
0
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0
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ARM;NYSTAD JORN;HUGOSSON
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OLA;FLORDAL OSKAR
0
○
登録記録あり
0
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登録記録あり
2
○
登録記録あり
1
○
登録記録あり
0
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ARM;REID ALASTAIR DAVID
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0
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ARM
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2
○
ARM
登録記録あり
0
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ARM
登録記録あり
1
○
ARM;REID ALASTAIR DAVID
登録記録あり
0
○
ARM
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
ARM;IDGUNJI SACHIN
SATISH;SANDHU BAL S
ARM
ARM;MACE TIMOTHY
CHARLES;CRAWFORD ASHLEY
JOHN
ARM;GRISENTHWAITE RICHARD
ROY;SEAL DAVID JAMES
ARM;HARDAGE JAMES
NOLAN;BLASCO ALLUE
CONRADO;HARRIS GLEN
ANDREW
ARM;GREENHALGH PETER
RICHARD;ROSE ANDREW
CHRISTOPHER
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No.
公報番号
出願日
タイトル (英語)
出願人
Error recovery upon reaching oldest instruction marked
with error or upon timed expiration by flushing
2011/12/23
instructions in pipeline pending queue and restarting
execution
152
US9075621B2
153
US9064561B2
2012/4/2 Handling of write operations within a memory device
154
US9070431B2
155
US9064559B2
156
US9042188B2
2013/10/25 Memory circuitry with write assist
Memory device and method of performing access
2013/8/15
operations within such a memory device
Memory controller and method of calibrating a memory
2013/4/1
controller
審査･権利状況被引用回数外国出願
ARM;SCHON
GUILLAUME;TEYSSIER MéLANIE
EMANUELLE LUCIE;PIRY
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FREDERIC CLAUDE
MARIE;SCALABRINO LUCA;BULL
DAVID MICHAEL
ARM;HOLD BETINA
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4
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ARM
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0
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ARM
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ARM
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0
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ARM;PIRY FREDERIC CLAUDE
MARIE;SCALABRINO
LUCA;SCHON
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GUILLAUME;TEYSSIER MELANIE
EMANUELLE LUCIE
0
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ARM;REID ALASTAIR DAVID
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0
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0
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0
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157
US9052909B2
2011/12/7 Recovering from exceptions and timing errors
158
US9021233B2
2011/9/28
159
US9041723B2
160
US9037835B1
2013/10/24 Data processing method and apparatus for prefetching
ARM;NYSTAD JORN;LASSEN
ANDERS
ARM
161
US9047092B2
2012/12/21 Resource management within a load store unit
ARM
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162
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US9032188B2
ARM
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ARM;ÖZER EMRE;BILES STUART
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DAVID
0
163
2012/10/17 Handling interrupts in a multi-processor system
Issue policy control within a multi-threaded in-order
2008/3/27
superscalar processor
0
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164
US9021172B2
0
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165
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0
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166
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0
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167
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0
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168
US9058179B2
0
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Interleaving data accesses issued in response to vector
access instructions
2012/5/4 Method of and apparatus for encoding and decoding data
Data processing apparatus and method and method for
ARM;HORSNELL MATTHEW
2012/7/6 generating performance monitoring interrupt signal based JAMES;EMMONS CHRISTOPHER 登録記録あり
on first event counter and second event counter
DANIEL
ARM;KALKUNTE
SHESHADRI;WILLIAMS MICHAEL 登録記録あり
JOHN
ARM;NYSTAD JORN;LASSEN
2012/5/4 Method of and apparatus for encoding and decoding data
登録記録あり
ANDERS
Apparatus and method for performing a convert-toARM;LUTZ DAVID
2012/5/11
登録記録あり
integer operation
RAYMOND;BURGESS NEIL
Retirement serialisation of status register access
2010/11/12
ARM;HARDAGE JAMES NOLAN 登録記録あり
operations
2012/8/2 Debug barrier transactions
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No.
公報番号
出願日
169
US9057761B2
2011/12/30
170
US9047184B2
2012/7/13
171
US9036427B2
2013/7/16
172
US9021298B2
2013/12/30
173
US8976177B2
2012/2/28
174
US9009208B2
2012/6/28
175
US9014496B2
2012/8/3
176
US8977837B2
2009/5/27
177
US8977815B2
2010/11/29
178
US8990282B2
2009/9/21
179
US8988443B2
2010/9/24
180
US8977820B2
2007/12/21
181
US9009450B2
2012/1/19
182
US9015719B2
2012/2/27
183
US9015424B2
2012/8/15
184
US9007855B2
2012/12/24
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;WHATMOUGH PAUL
Sensing supply voltage swings within an integrated circuit NICHOLAS;BULL DAVID
登録記録あり
MICHAEL;DAS SHIDHARTHA
ARM;BULL DAVID MICHAEL;DAS
Processing error detection within pipeline circuitry
登録記録あり
SHIDHARTHA;WHATMOUGH
PAUL NICHOLAS
Apparatus and a method for erasing data stored in a
ARM
登録記録あり
memory device
Integrated circuit with error repair and fault tolerance
ARM
登録記録あり
ARM;NYSTAD
Graphics processing
登録記録あり
JORN;CHRISTENSEN ASKE
SIMON
Floating-point adder
ARM;NYSTAD JORN
登録記録あり
ARM;NYSTAD JORN;FLORDAL
Methods of and apparatus for encoding and decoding
登録記録あり
OSKAR;DAVIES
data in data processing systems
JEREMY;HUGOSSON OLA
ARM;MCDONALD ROBERT
Apparatus and method for early issue and recovery for a
登録記録あり
GREGORY;MEYER PAUL
conditional load instruction having multiple outcomes
GILBERT
ARM;HEGGELUND FRODE;HOLM
Control of entry of program instructions to a fetch stage RUNE;ENGH-HALSTVEDT
登録記録あり
within a processing pipepline
ANDREAS DUE;FEILDING
EDVARD
Apparatus and method for performing fused multiply add
ARM;LUTZ DAVID RAYMOND
登録記録あり
floating point operation
ARM;CROXFORD
Methods of and apparatus for controlling the reading of
登録記録あり
DAREN;ERICSSON
arrays of data from memory
LARS;OTERHALS JON ERIK
ARM;PENTON ANTONY
JOHN;WAUGH ALEX
Handling of hard errors in a cache of a data processing
JAMES;ROSE ANDREW
登録記録あり
apparatus
CHRISTOPHER;HUGHES PAUL
STANLEY
Mixed operand size instruction processing for execution
ARM;STEPHENS NIGEL
登録記録あり
of indirect addressing load instruction specifying
JOHN;SEAL DAVID JAMES
registers for different size operands
Scheduling of tasks to be performed by a non-coherent
ARM;ELLIOTT ROBERT
登録記録あり
device
Write transaction management within a memory
ARM;MACE TIMOTHY CHARLES 登録記録あり
interconnect
Data signal receiver and method of calibrating a data
ARM
登録記録あり
signal receiver
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No.
公報番号
出願日
185
US9003123B2
2012/6/26
186
US8995191B2
2013/9/13
187
US8990518B2
2011/8/4
188
US8988954B2
2012/9/13
189
US8978038B2
2013/6/4
190
US8954711B2
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
Data processing apparatus and method for reducing
storage requirements for temporary storage of data
Memory device and a method of operating such a
memory device in a speculative read mode
Methods of and apparatus for storing data in memory in
data processing systems
Memory device and method of performing a read
operation within such a memory device
Data processing apparatus and method for processing a
received workload in order to generate result data
ARM;WAUGH ALEX
JAMES;WINROW MATTHEW LEE
登録記録あり
0
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ARM
登録記録あり
0
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0
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1
○
2012/1/30 Address generation in a data processing apparatus
US8971133B1
192
US8949844B2
193
US8954715B2
2012/3/16 Thread selection for multithreaded processing
194
US8966282B2
195
US8965945B2
2012/9/26 Cryptographic support instructions
Apparatus and method for performing floating point
2011/2/17
addition
197
US8966309B2
US8935592B2
ARM
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0
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ARM;STEPHENS NIGEL
JOHN;SEAL DAVID JAMES
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0
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登録記録あり
2
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登録記録あり
0
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ARM;VASEKIN VLADIMIR;ROSE
ANDREW
登録記録あり
CHRISTOPHER;SKILLMAN ALLAN
JOHN;PENTON ANTONY JOHN
0
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ARM
登録記録あり
0
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ARM;LUTZ DAVID RAYMOND
登録記録あり
0
○
ARM;SWAINE ANDREW
BROOKFIELD
登録記録あり
0
○
ARM
登録記録あり
0
○
0
○
0
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1
○
0
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0
○
Memory device and method of operation of such a
2013/9/26
ARM
memory device
Hardware resource management within a data processing ARM;WILLIAMS MICHAEL
2010/9/13
system
JOHN;BILES STUART DAVID
191
196
ARM;NYSTAD JORN;HUGOSSON
登録記録あり
OLA
ARM;CHONG YEW K;MANGAL
登録記録あり
SANJAY
2011/6/28 Distribution of an incrementing count value
Apparatus and method for correcting errors in data
2012/11/20
accessed from a memory device
198
US8959318B2
2011/6/28
199
US8957703B2
2010/4/5
200
US8959472B1
2013/9/27
201
US8943118B2
2012/7/31
202
US8963609B2
2013/3/1
ARM;GRISENTHWAITE RICHARD
Illegal mode change handling
登録記録あり
ROY
ARM;RIEN MIKAEL;DUBY JEANProtecting lower voltage domain devices during operation CLAUDE;LEYMARIE
登録記録あり
in a higher voltage domain
FLORA;BLANC
FABRICE;PADILLA THIERRY
Considering compatibility of adjacent boundary regions
ARM
登録記録あり
for standard cells placement and routing
Data processing apparatus and method for reducing the ARM;BURGESS NEIL;LUTZ DAVID
登録記録あり
size of a lookup table
RAYMOND
Combinatorial circuit and method of operation of such a
ARM
登録記録あり
combinatorial circuit
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No.
公報番号
出願日
203
US8959131B2
2011/9/22
204
US8941428B2
2014/4/9
205
US8972701B2
2011/12/6
206
US8966494B2
2012/3/16
207
US8966323B2
2010/12/23
208
US8966228B2
2009/3/20
209
US8965946B2
2011/7/19
210
US8959304B2
2013/2/26
211
US8949547B2
2011/8/8
212
US8947968B2
2013/7/8
213
US8935485B2
2011/8/8
214
US8914616B2
2011/12/2
215
US8922568B2
2011/6/9
216
US8922247B2
2010/11/22
217
US8898430B2
2012/12/5
タイトル (英語)
出願人
ARM;NYSTAD JORN;ENGHNumber format pre-conversion instructions
HALSTVEDT ANDREAS
DUE;CHARLES SIMON ALEX
Low power latching circuits
ARM
Setting zero bits in architectural register for storing
ARM;HARDAGE JAMES
destination operand of smaller size based on
NOLAN;HARRIS GLEN
corresponding zero flag attached to renamed physical
ANDREW;GLASS MARK
register
CARPENTER
ARM;MAKLJENOVIC
Apparatus and method for processing threads requiring
NEBOJSA;JAMES BENJAMIN
resources
CHARLES
Monitoring multiple data transfers
ARM;HORLEY JOHN MICHAEL
ARM;CRASKE SIMON
Instruction fetching following changes in program flow
JOHN;PATHIRANE CHILODA
ASHAN SENERATH
Data processing apparatus and method for performing a ARM;LUTZ DAVID
reciprocal operation on an input value to produce a result RAYMOND;HINDS CHRISTOPHER
value
NEAL
Management of data processing security in a secondary
ARM
processor
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
Coherency controller and method for data hazard
JAMSHED;PRASADH
handling for copending data access requests
RAMAMOORTHY GURU;FILIPPO
MICHAEL ALAN
Memory having power saving mode
ARM
ARM;JALAL JAMSHED;FEERO
BRETT STANLEY;WERKHEISER
Snoop filter and non-inclusive shared cache memory
MARK DAVID;FILIPPO MICHAEL
ALAN
Exchanging physical to logical register mapping for
obfuscation purpose when instruction of no operational ARM;CRASKE SIMON JOHN
impact is executed
ARM;JONES SIMON;ENGHSwitching between dedicated function hardware and use HALSTVEDT
of a software routine to generate result data
ANDREAS;CHRISTENSEN ASKE
SIMON
ARM;MYERS JAMES
Power controlling integrated circuit and retention
EDWARD;FLYNN DAVID
switching circuit
WALTER;BIGGS JOHN PHILIP
Fault handling in address translation transactions
ARM
Copyright 2016 Innovation Research Corporation
審査･権利状況被引用回数外国出願
登録記録あり
2
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0
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0
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0
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0
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0
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0
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1
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1
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0
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0
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0
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0
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No.
公報番号
218
US8922572B2
2012/9/20 Occlusion queries in graphics processing
登録記録あり
0
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219
US8928668B2
2009/10/6
登録記録あり
1
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220
US8928667B2
2009/10/6
登録記録あり
1
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221
US8924615B2
2012/10/26
登録記録あり
0
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222
US8892623B2
2012/6/14
登録記録あり
0
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223
US8930601B2
2012/2/27
登録記録あり
2
○
224
US8924766B2
2012/2/28
ARM;PELLOIE JEAN
登録記録あり
LUC;LAPLANCHE YVES THOMAS
0
○
225
US8924686B2
2009/10/8 Memory management unit
ARM;PERSSON ERIK;HUGOSSON
登録記録あり
OLA;BJöRKLUND ANDREAS
0
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226
US8924612B2
ARM;MAJI PARTHA
PRASUN;MELLOR STEVEN
RICHARD
登録記録あり
0
○
227
US8918700B2
ARM
登録記録あり
0
○
ARM;HARRIS GLEN
ANDREW;HARDAGE JAMES
NOLAN;GLASS MARK
CARPENTER
登録記録あり
0
○
ARM;HUGHES PAUL
STANLEY;PARKER JASON
登録記録あり
0
○
ARM;TUNE ANDREW DAVID
登録記録あり
0
○
ARM
登録記録あり
1
○
ARM
登録記録あり
4
○
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
2
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228
US8914615B2
229
US8892923B2
230
US8892801B2
231
US8891886B2
232
US8885429B1
233
US8856408B2
出願日
タイトル (英語)
出願人
ARM
ARM;NYSTAD JORN;HOLM
Method and apparatus for rendering a stroked curve for
RUNE;CHRISTENSEN ASKE
display in a graphics processing system
SIMON
ARM;NYSTAD JORN;HOLM
Rendering stroked curves in graphics processing systems RUNE;CHRISTENSEN ASKE
SIMON
Communication of message signalled interrupts
ARM
ARM;BURGESS NEIL;LUTZ DAVID
Data processing apparatus and method
RAYMOND
Transaction routing device and method for routing
ARM;LAUGHTON ARTHUR
transactions in an integrated circuit
Analysing timing paths for circuits formed of standard
cells
Apparatus and method for providing a bidirectional
2012/4/4 communications link between a master device and a
slave device
Apparatus and method for controlling access to a
2013/2/11
memory device
Mapping same logical register specifier for different
2011/12/2 instruction sets with divergent association to
architectural register file using common address format
Data processing apparatus and method for maintaining a
2011/12/20 time count value in normal and power saving modes of
operation
Arbitration circuity and method for arbitrating between a
2012/5/23
plurality of requests for access to a shared resource
2012/9/28 Method of and apparatus for encoding data
Memory device and a method for erasing data stored in
2013/6/12
the memory device
2010/10/5
Reduced latency barrier transaction requests in
interconnects
Copyright 2016 Innovation Research Corporation
審査･権利状況被引用回数外国出願
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
234
US8874975B2
235
US8874883B2
236
US8881078B2
237
US8873209B2
238
US8848412B1
239
US8887001B2
240
US8868962B2
241
US8862935B2
2013/12/30 Integrated circuit with error repair and fault tolerance
242
US8831341B2
2011/10/5 Image encoding using base colors on luminance line
243
US8839038B2
2012/2/14 Diagnosing code using single step execution
244
US8819309B1
245
US8819378B2
2011/10/13 Tracing of a data processing apparatus
2011/7/28 Debugging of a data processing apparatus
2013/2/6 Proprietary circuit layout identification
Integrated circuit and method of providing electrostatic
2011/12/19
discharge protection within such an integrated circuit
2013/7/5 Ternary content addressable memory
2011/2/14 Trace data priority selection
2012/2/8 Monitoring circuit and method
2013/6/14 Low latency bypass buffer
Data processing apparatus and method for performing
2011/11/14 memory transactions within such a data processing
apparatus
246
US8803898B2
2009/12/17 Forming a windowing display in a frame buffer
247
US8812997B2
2011/5/18 Structural feature formation within an integrated circuit
248
US8824215B2
2012/2/1 Data storage circuit that retains state during precharge
249
US8839057B2
2011/2/3
審査･権利状況被引用回数外国出願
ARM;GILKERSON PAUL
ANTHONY;HORLEY JOHN
登録記録あり
MICHAEL;GIBBS MICHAEL JOHN
0
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0
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1
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3
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0
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0
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0
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ARM;BERENT ANTHONY NEIL
登録記録あり
ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD 登録記録あり
ROY
ARM
登録記録あり
0
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2
○
4
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ARM;CRASKE SIMON JOHN
0
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4
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0
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0
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1
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ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD
ROY
ARM
ARM;BLANC FABRICE;PAULY
MATTHIEU;POTTIER FLORA
ARM
ARM;HORLEY JOHN
MICHAEL;WILLIAMS MICHAEL
JOHN;KNEEBONE KATHERINE
ELIZABETH;REID ALASTAIR
DAVID
ARM;MYERS JAMES
EDWARD;FLYNN DAVID
WALTER;SANDHU BAL S
ARM
登録記録あり
ARM;SHREINER DAVID
ROBERT;DEVEREUX IAN
VICTOR;SøRG{DOT OVER (A)}RD 登録記録あり
EDVARD;OLSON THOMAS
JEREMY
ARM;YERIC GREGORY MUNSON 登録記録あり
ARM;FREDERICK JR. MARLIN
登録記録あり
WAYNE;ALAM AKHTAR
WASEEM;PAL SUMANA
Integrated circuit and method for testing memory on the
ARM;HUGHES PAUL STANLEY
integrated circuit
Copyright 2016 Innovation Research Corporation
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No.
250
公報番号
US8838929B2
出願日
タイトル (英語)
Allocation and deallocation of bounded time relative
2011/10/5
portions of a graphics memory
251
US8830783B2
2011/1/3 Improving read stability of a semiconductor memory
252
US8826097B2
253
US8826079B2
254
US8817433B2
255
US8775754B2
256
US8788775B2
257
US8766991B2
258
US8788887B2
259
US8775824B2
260
US8762744B2
261
US8769251B2
262
US8769307B2
2005/6/1 Secure operation indicator
263
US8799621B2
2013/8/8 Translation table control
264
US8782378B2
2011/3/30 Memory scrubbing
出願人
審査･権利状況被引用回数外国出願
ARM;FELL ROBIN
登録記録あり
0
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2
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0
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4
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0
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2
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2
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0
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1
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0
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ARM;LUC PHILIPPE;LATAILLE
NORBERT BERNARD EUGé
登録記録あり
NE;BEGON
FLORENT;CHAUSSADE NICOLAS
0
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0
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0
○
0
○
ARM;IDGUNJI SACHIN
SATISH;GAJJEWAR HEMANGI
UMAKANT;SCHUPPE VINCENT
登録記録あり
PHILLIPE;CHONG YEW
KEONG;CHEN HSIN-YU
ARM;ÖZER EMRE;IDGUNJI
登録記録あり
SACHIN SATISH
ARM;GILDAY DAVID
登録記録あり
MICHAEL;CRASKE SIMON JOHN
Data processing apparatus and method for identifying
debug events
Electrostatic discharge protection device having an
ARM;PADILLA THIERRY;BLANC
2011/7/28 intermediate voltage supply for limiting voltage stress on
FABRICE;DUBY JEAN-CLAUDE
components
ARM;CAMPBELL MICHAEL
Memory controller and method of selecting a transaction ANDREW;WRIGLEY
2011/6/24
using a plurality of ordered lists
CHRISTOPHER EDWIN;FEERO
BRETT STANLEY
Memory access control using redundant and nonARM;GRISENTHWAITE RICHARD
2011/6/28
redundant encoding
ROY
Processing order with integer inputs and floating point
ARM;ENGH-HALSTVEDT
2011/5/25
inputs
ANDREAS DUE;NYSTAD JøRN
ARM;GILKERSON PAUL
Data processing apparatus, trace unit and diagnostic
2011/8/3
ANTHONY;HORLEY JOHN
apparatus
MICHAEL
Protecting the security of secure data sent from a
ARM;KERSHAW DANIEL;PAVER
2008/1/2 central processor for processing by a further processing
NIGEL CHARLES
device
ARM;FORD SIMON
Energy management system configured to generate
ANDREW;BRADLEY DARYL
2008/6/3 energy management information indicative of an energy
WAYNE;MILNE GEORGE
state of processing elements
JAMES;HORLEY JOHN MICHAEL
2011/12/16
2006/12/13
Data processing apparatus and method for converting
data values between endian formats
2010/9/14 Dynamic instruction splitting
ARM;FELTON DONALD;MCNIVEN
登録記録あり
JAMES I
ARM
登録記録あり
ARM;CHAUSSADE
登録記録あり
NICOLAS;TEYSSIER RéMI
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No.
265
公報番号
US8780655B1
266
US8779787B2
267
US8773593B2
268
US8773185B2
269
US8769344B2
出願日
タイトル (英語)
Method and apparatus for aligning a clock signal and a
2012/12/24
data strobe signal in a memory system
Apparatus and method for determining variation in a
2011/11/16
predetermined physical property of a circuit
2011/1/3 Noise reduction filter circuitry and method
2012/11/20 Calibration of delay chains
2011/6/13 Tracing speculatively executed instructions
270
US8732400B2
2010/10/5 Data store maintenance requests in interconnects
271
US8732499B2
2011/5/27
272
US8719555B2
273
US8719553B2
274
US8717366B2
State retention circuit adapted to allow its state integrity
to be verified
Method for overcoming livelock in a multi-threaded
2008/1/31
system
Method for re-circulating a fragment through a rendering
2008/1/31
pipeline
2010/7/27 Method and apparatus for rendering a stroked curve
275
US8725953B2
2009/1/21
276
US8743135B2
2009/10/6
277
US8756377B2
2010/2/2
278
US8751833B2
2010/4/30
279
US8742827B2
2011/5/24
280
US8738971B2
2011/12/7
281
US8732523B2
2011/10/24
出願人
審査･権利状況被引用回数外国出願
ARM
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0
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2
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0
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0
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登録記録あり
2
○
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
2
○
ARM;FLYNN DAVID WALTER
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0
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0
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0
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0
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4
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0
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0
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2
○
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0
○
登録記録あり
2
○
登録記録あり
0
○
ARM;LAPLANCHE YVES
THOMAS
ARM;PERSSON ERIK;EDGREN
PER
ARM
ARM;GILKERSON PAUL
ANTHONY;HORLEY JOHN
MICHAEL
ARM NORWAY AS;NYSTAD
JORN;HEGGELUND FRODE
ARM NORWAY AS;NYSTAD
JORN;HEGGELUND FRODE
ARM;MERRY BRUCE
ARM;PAVER NIGEL C;BILES
Local cache power control within a multiprocessor
STUART D;WELTON KEVIN
system
P;MEYER PAUL G
Graphics processing systems
ARM;NYSTAD JøRN;HOLM RUNE
ARM;CRASKE SIMON
JOHN;PENTON ANTONY
Area and power efficient data coherency maintenance
JOHN;PIERRON LOIC;ROSE
ANDREW CHRISTOPHER
Data processing system
ARM;HILL STEPHEN JOHN
ARM;VAN WINKELHOFF
Power gating circuit
NICOLAAS KLARINUS
JOHANNES;BRUN MIKAEL
ARM;PIRY FREDERIC CLAUDE
Limiting certain processing activities as error rate
MARIE;SCALABRINO LUCA;BULL
probability rises
DAVID MICHAEL
Data processing apparatus and method for analysing
ARM;ÖZER EMRE;SAZEIDES
transient faults occurring within storage elements of the YIANNAKIS;KERSHAW
data processing apparatus
DANIEL;BILES STUART DAVID
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No.
公報番号
出願日
タイトル (英語)
出願人
282
US8717084B1
2012/12/6 Post fabrication tuning of an integrated circuit
登録記録あり
0
○
283
US8717078B2
2012/6/13
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4
○
284
US8707056B2
2011/9/21
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34
○
285
US8713371B2
2011/11/15
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0
○
286
US8677107B2
2011/3/7
登録記録あり
2
○
287
US8698828B2
2009/6/3
登録記録あり
0
○
288
US8707106B2
2011/6/9
登録記録あり
0
○
289
US8713375B2
2011/5/13
登録記録あり
0
○
290
US8706936B2
2011/11/14
登録記録あり
3
○
291
US8706965B2
Apparatus and method for handling access operations
ARM;PIRY FREDERIC
2011/6/3 issued to local cache structures within a data processing CLAUDE;MOUTON LOUIS-MARIE 登録記録あり
apparatus
VINCENT;SCALABRINO LUCA
0
○
0
○
4
○
1
○
登録記録あり
0
○
ARM;SAZEIDES YIANNAKIS;ÖZER
EMRE;KERSHAW DANIEL;BRELOT 登録記録あり
JEAN-BAPTISTE
3
○
ARM
ARM;IDGUNJI SACHIN
Sequential latching device with elements to increase hold
SATISH;AITKEN ROBERT
times on the diagnostic data path
CAMPBELL;IQBAL IMRAN
Security provision for a subject image displayed in a nonARM;FELTON DONALD
secure domain
ARM;WILLIAMS MICHAEL
Controlling generation of debug exceptions
JOHN;GRISENTHWAITE RICHARD
ROY
ARM;GRISENTHWAITE RICHARD
Apparatus and method for handling exception events
ROY
ARM;PLOWMAN
Graphics processing systems
EDWARD;NYSTAD Jø
RN;LJOSLAND BORGAR
ARM;HORLEY JOHN M;SWAINE
Key allocation when tracing data processing systems
ANDREW B;GILKERSON PAUL A
ARM;GILKERSON PAUL
Correlating trace data streams
ANTHONY;HORLEY JOHN
MICHAEL
Integrated circuit having a bus network, and method for ARM;PRASADH RAMAMOORTHY
the integrated circuit
GURU
System for efficiently tracing data in a data processing
2010/12/27
system
292
US8677104B2
293
US8681168B2
294
US8698820B2
2009/6/5 Graphics processing systems
295
US8713292B2
Reducing energy and increasing speed by an instruction
2011/2/7 substituting subsequent instructions with specific
function instruction
296
US8694862B2
2010/1/12 Methods of and apparatus for processing graphics
2012/4/20
Data processing apparatus using implicit data storage
data storage and method of implicit data storage
審査･権利状況被引用回数外国出願
ARM;GIBBS
MICHAEL;GILKERSON PAUL
登録記録あり
ANTHONY;HORLEY JOHN
MICHAEL
ARM;NYSTAD JøRN;LANGTIND
FRANK;TAPPLY JOE;CROXFORD 登録記録あり
DAREN
ARM;COX ANDREW
登録記録あり
HELGE;ELLIOT ROBERT;FELL
ROBIN;ELLIS SEAN
ARM;NYSTAD JORN
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No.
公報番号
297
US8680912B2
298
US8680900B2
299
US8675681B2
300
US8675006B2
301
US8645893B1
302
US8639960B2
2011/5/27 Verifying state integrity in state retention circuits
303
US8665009B2
2012/7/31
Integrated circuit and method for controlling load on the
output from on-chip voltage generation circuitry
304
US8661225B2
2010/1/19
Data processing apparatus and method for handling
vector instructions
305
US8648654B1
2012/9/25
Integrated circuit and method for generating a layout of
such an integrated circuit
306
US8638157B2
2011/5/23 Level shifting circuitry
307
US8650470B2
308
US8656078B2
309
US8667199B2
310
US8661232B2
出願日
タイトル (英語)
2012/7/17 Level shifting circuitry
Self-initializing on-chip data processing apparatus and
2012/8/10 method of self-initializing an on-chip data processing
apparatus
Communication within an integrated circuit including an
2011/7/7
array of interconnected programmable logic elements
2009/8/11
Apparatus and method for communicating between a
central processing unit and a graphics processing unit
Method of generating a layout of an integrated circuit
2012/10/23 comprising both standard cells and at least one memory
instance
2010/10/25 Error recovery within integrated circuit
Transaction identifier expansion circuitry and method of
operation of such circuitry
Data processing apparatus and method for performing
2008/3/18
multi-cycle arbitration
2011/5/9
2010/9/16 Register state saving and restoring
出願人
審査･権利状況被引用回数外国出願
ARM;REED BRIAN WILLIAM
登録記録あり
1
○
ARM;WANG BINGDA
BRANDON;GITCHEV KOSTADIN
登録記録あり
0
○
0
○
2
○
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8
○
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0
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0
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1
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4
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0
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0
○
登録記録あり
4
○
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0
○
登録記録あり
0
○
ARM;HILL STEPHEN
登録記録あり
JOHN;MULLER MICHAEL PETER
ARM;FORD SIMON
ANDREW;ELLIS SEAN
登録記録あり
TRISTRAM;PLOWMAN EDWARD
CHARLES
ARM
ARM;FLYNN DAVID
WALTER;IDGUNJI SACHIN
SATISH
ARM;MYERS JAMES
EDWARD;SAVANTH
PARAMESHWARAPPA ANAND
KUMAR;FLYNN DAVID
WALTER;HOWARD DAVID
WILLIAM;SANDHU BAL S
ARM;BJöRKLUND
ANDREAS;PERSSON
ERIK;HUGOSSON OLA
ARM
ARM;DUBY JEAN-CLAUDE;RIEN
MIKAEL;GUYONNET DAMIEN
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;FLAUTNER
KRISZTIAN;AUSTIN TODD
MICHAEL;BLAAUW DAVID
THEODORE;MUDGE TREVOR
NIGEL;BULL DAVID
ARM;LIM SEOW CHUAN
ARM;GWILT DAVID
JOHN;INGRAM GRAEME LESLIE
ARM;PENTON ANTONY
JOHN;AXFORD SIMON
Copyright 2016 Innovation Research Corporation
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No.
公報番号
出願日
タイトル (英語)
出願人
311
US8660173B2
2010/10/7 Video reference frame retrieval
312
US8640008B2
313
US8639987B2
314
US8639975B2
315
US8638622B2
316
US8635411B2
317
US8635406B2
318
US8634440B2
2010/8/23 Time-division multiplexing processing circuitry
319
US8630358B2
2012/3/20
2011/12/23 Error recovery in a data processing apparatus
2011/2/18
Data processing apparatus and method using monitoring
circuitry to control operating parameters
2010/11/17 Error management within a data processing system
Apparatus and method for receiving a differential data
strobe signal
Data processing apparatus and method for managing
2011/7/18
coherency of cached data
Data processing apparatus and method for providing
2012/3/8
target address information for branch instructions
2011/7/6
Data packet flow control across an asynchronous clock
domain boundary
320
US8607006B2
2010/10/5 Barrier transactions in interconnects
321
US8621242B2
322
US8621272B2
2010/7/7 Integrated circuit with error repair and fault tolerance
323
US8621336B2
2008/8/1 Error correction in a set associative storage device
2010/10/14 Display of a verification image to confirm security
ARM;BJöRKLUND
ANDREAS;PERSSON ERIK;BORG
PONTUS;WALLANDER MATS
PETTER
ARM;SCHON
GUILLAUME;SCALABRINO
LUCA;PIRY FREDERIC CLAUDE
MARIE;BULL DAVID MICHAEL
ARM;WHATMOUGH PAUL
NICHOLAS;BULL DAVID
MICHAEL;DAS SHIDHARTHA
ARM;WHATMOUGH PAUL
NICHOLAS;BULL DAVID
MICHAEL;DAS
SHIDHARTHA;KERSHAW DANIEL
ARM;WANG BINGDA B;GITCHEV
KOSTADIN
ARM;FLANDERS WILLIAM
HENRY;KHOSA VIKRAM
ARM;GREENHALGH PETER
R;CRASKE SIMON J
ARM;SAUNDERS SPENCER
J;DILLON LIAM;JANTA RAFAL J
ARM;MAJI PARTHA
PRASUN;MELLOR STEVEN
RICHARD
審査･権利状況被引用回数外国出願
登録記録あり
0
○
登録記録あり
0
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4
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2
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登録記録あり
3
○
登録記録あり
0
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登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
0
○
登録記録あり
5
○
登録記録あり
8
○
登録記録あり
0
○
ARM;BROWN ROBERT;FELTON
DONALD;MCNIVEN JAMES IAN
ARM;DAS SHIDHARTHA;BULL
DAVID MICHAEL;OZER EMRE
ARM;CRASKE SIMON
JOHN;ROSE ANDREW
CHRISTOPHER;HUGHES PAUL
STANLEY;PENTON ANTONY
JOHN;YORK RICHARD;FORD
SIMON ANDREW;BILES STUART
DAVID;WAUGH ALEX JAMES
Copyright 2016 Innovation Research Corporation
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外国出願あり（各国）
No.
324
公報番号
US8619554B2
出願日
タイトル (英語)
出願人
2006/8/4 Interconnecting initiator devices and recipient devices
0
○
登録記録あり
2
○
登録記録あり
0
○
ARM;RIOCREUX PETER ANDREW 登録記録あり
2
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
5
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
ARM;PIRY FREDERIC CLAUDE
MARIE;MOUTON LOUIS-MARIE
Apparatus and method for mapping architectural registers
2010/6/15
VINCENT;SCALABRINO
登録記録あり
to physical registers
LUCA;GRISENTHWAITE RICHARD
ROY;MANSELL DAVID HENNAH
1
○
325
US8615687B2
326
US8611172B2
2012/5/21
Controlling a voltage level of an access signal to reduce
access disturbs in semiconductor memories
327
US8601167B2
2010/10/13
Maintaining required ordering of transaction requests in
interconnects using barriers and hazard checks
Checkpointing long latency instruction as fake branch in
branch prediction mechanism
328
US8578139B2
2010/8/5
329
US8594177B2
2010/8/31
330
US8566563B2
2011/3/14 Translation table control
331
US8589934B2
332
US8589631B2
2011/9/12 Coherency control with writeback ordering
333
US8589927B2
2011/2/14
334
US8583897B2
2009/2/2
US8578136B2
審査･権利状況被引用回数外国出願
登録記録あり
Data processing system and method for regulating a
2011/1/10 voltage supply to functional circuitry of the data
processing system
335
ARM;TUNE ANDREW
DAVID;HOTCHKISS ROBIN
ARM;SANDHU BAL S;IDGUNJI
SACHIN SATISH;FLYNN DAVID
WALTER
ARM;SHYANMUGAM
AMARANTH;MAITI
BIKAS;SCHUPPE VINCENT
PHILLIPE;CHONG YEW
KEONG;KINKADE MARTIN
JAY;CHEN HSIN-YU
2011/4/1
Reducing reference frame data store bandwidth
requirements in video decoders
Controlling priority levels of pending threads awaiting
processing
Method, apparatus and trace module for generating
timestamps
ARM;CHAUSSADE
NICOLAS;BEGON
FLORENT;TEYSSIER MéLANIE
EMANUELLE LUCIE;TEYSSIER Ré
MI;JAUBERT JOCELYN
FRANCOIS ORION
ARM;BJöRKLUND
ANDREAS;HUGOSSON OLA
ARM;GRISENTHWAITE RICHARD
ROY
ARM;MAKLJENOVIC
NEBOJSA;FIELDING
EDVARD;ENGH-HALSTVEDT
ANDREAS
ARM;LAYCOCK CHRISTOPHER
WILLIAM;HARRIS ANTONY
JOHN;MATHEWSON BRUCE
JAMES;BILES STUART DAVID
ARM;WILLIAMS MICHAEL
JOHN;HORLEY JOHN
MICHAEL;ASHFIELD EDMOND
JOHN SIMON
Register file with circuitry for setting register entries to a
ARM;CRASKE SIMON JOHN
predetermined value
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
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No.
公報番号
出願日
2010/10/29
タイトル (英語)
出願人
Apparatus and method for performing multiplyaccumulate operations
336
US8595280B2
337
US8572329B2
2005/10/4 Multi-region default memory map
338
US8601485B2
2011/5/25
339
US8601324B2
340
US8599626B2
Data processing apparatus and method for processing a
received workload in order to generate result data
2010/8/2 Storage and output of trace data
2011/12/7
Memory device and a method of operating such a
memory device in a speculative read mode
Terminating barriers in streams of access requests to a
data store while maintaining data consistency
341
US8589638B2
2011/7/19
342
US8582389B2
2011/6/15 Write assist in a dual write line semiconductor memory
343
US8582340B2
2012/1/12
Word line and power conductor within a metal layer of a
memory cell
344
US8561169B2
2007/12/5
Data processing apparatus and method for managing
access to a display buffer
345
US8533685B2
2011/10/26
346
US8549199B2
2010/9/15
347
US8548962B2
2011/8/15
348
US8533505B2
2010/3/1
349
US8532192B2
2010/7/14
350
US8549325B2
2008/5/2
Processing apparatus, trace unit and diagnostic
apparatus
Data processing apparatus and a method for setting
priority levels for transactions
Data compression and decompression using relative and
absolute delta values
Data processing apparatus and method for transferring
workload between source and destination processing
circuitry
Video processing apparatus and a method of processing
video data
Reducing information leakage between processes sharing
a cache
ARM;SYMES DOMINIC
HUGO;WILDER MLADEN;LARRI
GUY
ARM;AXFORD SIMON;CRASKE
SIMON JOHN;KIMELMAN PAUL
ARM;ENGH-HALSTVEDT
ANDREAS DUE;NYSTAD JøRN
ARM;HORLEY JOHN
MICHAEL;HINDS CHRISTOPHER
NEAL
審査･権利状況被引用回数外国出願
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
3
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
5
○
ARM;MACE TIMOTHY CHARLES
登録記録あり
5
○
ARM;TAPPLY JOE D.;LILAND
EIVIND;ELLIS SEAN T.
登録記録あり
0
○
ARM;GREENHALGH PETER
RICHARD
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
1
○
ARM;HOLD BETINA
ARM;CAMPBELL MICHAEL
ANDREW;RIOCREUX PETER
ANDREW
ARM;GAJJEWAR HEMANGI
UMAKANT;IDGUNJI SACHIN
SATISH;YEUNG GUS
ARM;CHONG YEW
KEONG;YEUNG GUS
ARM;HARRIS PETER
WILLIAM;WILSON PETER
BRIAN;MARTIN DAVID
PAUL;THORNTON TIMOTHY
CHARLES
ARM;HORLEY JOHN
MICHAEL;CRASKE SIMON
JOHN;GIBBS MICHAEL
JOHN;GILKERSON PAUL
ANTHONY
ARM;PERSSON ERIK;EDSö
TOMAS
ARM;HARRIS PETER
WILLIAM;MARTIN DAVID PAUL
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;IDGUNJI SACHIN
Apparatus and method for detecting an approaching error SATISH;DAS SHIDHARTHA;BULL
2010/6/7
登録記録あり
condition
DAVID MICHAEL;AITKEN
ROBERT CAMPBELL
351
US8555124B2
352
US8549633B2
353
US8549257B2
354
US8542939B2
355
US8519775B2
356
US8502568B2
357
US8493810B2
358
US8493120B2
359
US8484497B2
2010/7/27 Power supply control within an integrated circuit
360
US8497702B2
2011/4/15
361
US8477148B2
362
US8468394B2
363
US8468393B2
2
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
3
○
登録記録あり
10
○
登録記録あり
1
○
登録記録あり
0
○
登録記録あり
5
○
ARM;PATIL SANJAY
BHAGWAN;GOMEZ
登録記録あり
VALENTINA;SEBASTINE ANTONY
6
○
登録記録あり
2
○
登録記録あり
4
○
登録記録あり
0
○
登録記録あり
2
○
ARM;CHUAN LIM SEOW;MACE
TIMOTHY CHARLES
Area efficient arrangement of interface devices within an ARM;MISHRA VIKAS;WANG
2011/1/10
integrated circuit
BINGDA BRANDON
2011/8/3 Security controller
Methods of and apparatus for using tree representations
ARM;NYSTAD JORN;FLORDAL
2011/8/4 for representing arrays of data elements for encoding and
OSKAR;DAVIES JEREMY
decoding data in data processing systems
ARM;IDGUNJI SACHIN
SATISH;SANDHU BAL S
ARM;DWIVEDI SANDEEP;KUMAR
2010/8/17 Receiver circuit with high input voltage protection
NIDHIR;CHERUKU SRIDHAR
ARM;VAN WINKELHOFF
NICOLAAS KLARINUS
2011/5/9 Memory circuitry with write boost and write assist
JOHANNES;GOUYA GERALD
JEAN LOUIS;CHEN HSIN-YU
Storage circuitry and method with increased resilience to ARM;CHOUDHURY MIHIR
2011/3/10
single event upsets
RAJANIKANT;CHANDRA VIKAS
2011/7/28 Voltage regulation of a virtual power rail
Power control of an integrated circuit including an array
of interconnected configurable logic elements
2009/10/6 Graphics processing systems
ARM;HILL STEPHEN
JOHN;MULLER MICHAEL PETER
ARM;NYSTAD JøRN;HOLM RUNE
ARM;BRADLEY DARYL
Method of tracing selected activities within a data
WAYNE;HORLEY JOHN
2008/11/3 processing system by tagging selected items and tracing
MICHAEL;WOODHOUSE
the tagged items
SHELDON JAMES
ARM;HORLEY JOHN
Triggering diagnostic operations within a data processing
2007/6/28
MICHAEL;SWAINE ANDREW
apparatus
BROOKFIELD
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No.
公報番号
出願日
タイトル (英語)
出願人
Translation of SIMD instructions in a data processing
system
364
US8505002B2
2007/9/27
365
US8498373B2
2012/1/12 Generating a regularly synchronised count value
366
US8478947B2
367
US8479033B2
2010/6/16 Power supply detection circuitry and method
368
US8510356B2
2010/3/16 Identifier selection
369
US8509015B2
370
US8504961B2
371
US8502561B2
372
US8499106B2
373
US8499017B2
374
US8490107B2
2005/7/5 Memory controller
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;YEHIA
SAMI;FLAUTNER
KRISZTIAN;CLARK
NATHAN;HORMATI
AMIR;MAHLKE SCOTT
ARM;HORLEY JOHN
MICHAEL;WOODHOUSE
SHELDON JAMES;WILLIAMS
MICHAEL JOHN;KALKUNTE
SHESHADRI;ROSE ANDREW
CHRISTOPHER
ARM;INGRAM GRAEME
LESLIE;QUINN IAN JAMES
ARM;GAJJEWAR HEMANGI
UMAKANT;YEUNG GUS
ARM;HORLEY JOHN
MICHAEL;SWAINE ANDREW
BROOKFIELD;WILLIAMS
MICHAEL JOHN
Using a precharge characteristics of a node to validate a
2011/12/16 previous data/signal value represented by a discharge of ARM;HOLD BETINA K. M.
said node
2011/5/18 Integrated circuit with timing adjustment mechanism
ARM;JAVERLIAC VIRGILE
ARM;HOWARD DAVID
2011/7/1 Signal value storage circuitry with transition detector
WILLIAM;BULL DAVID
MICHAEL;DAS SHIDHARTHA
ARM;POUBLAN SERGE
2010/6/24 Buffering of a data stream
HENRI;SWAINE ANDREW
BROOKFIELD
ARM;PENTON ANTONY
Apparatus and method for performing fused multiply add
2009/8/12
JOHN;CRASKE SIMON
floating point operation
JOHN;CAULFIELD IAN MICHAEL
ARM;JALAL
JAMSHED;WERKHEISER MARK
DAVID;FEERO BRETT
Processing resource allocation within an integrated
STANLEY;FILIPPO MICHAEL
2011/8/8 circuit supporting transaction requests of different
ALAN;PRASADH
priority levels
RAMAMOORTHY
GURU;MANNAVA PHANINDRA
KUMAR
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375
US8488369B2
376
US8484508B2
377
US8473819B2
378
US8473717B2
379
US8471612B1
380
US8468405B2
381
US8448251B2
382
US8443170B2
383
US8463958B2
384
US8441301B2
385
US8421501B1
出願日
2011/3/10
タイトル (英語)
出願人
Method of altering distribution of a chosen characteristic ARM;CHANDRA VIKAS;AITKEN
of a plurality of memory cells forming a memory device
ROBERT CAMPBELL
ARM;PENTON ANTONY
Data processing apparatus and method for providing fault
JOHN;FORD SIMON
2010/1/14 tolerance when executing a sequence of data processing
ANDREW;ROSE ANDREW
operations
CHRISTOPHER
ARM;KERSHAW DANIEL;BULL
2011/3/24 Error management
DAVID MICHAEL;WILDER
MLADEN
Coprocessor reset controller with queue for storing
ARM;HUGOSSON OLA;PERSSON
2010/2/3 configuration information of subsequent sessions prior to
ERIK;BORG PONTUS
completion of current session
Signal value storage circuitry with transition error
ARM;BULL DAVID MICHAEL;DAS
2012/7/10
detector
SHIDHARTHA
ARM;MCLAURIN TERESA
2010/12/22 Integrated circuit testing
LOUISE;WILLIAMS GERARD
RICHARD
Method and apparatus for processing and displaying
ARM;HARRIS PETER
2009/3/25
secure and non-secure data
WILLIAM;MARTIN DAVID PAUL
ARM;WILDER MLADEN;SYMES
Apparatus and method for performing SIMD multiply2009/9/17
DOMINIC HUGO;BRUCE
accumulate operations
RICHARD EDWARD
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
JAMSHED;PRASADH
Dynamic resource allocation for transaction requests
2011/8/8
RAMAMOORTHY GURU;FILIPPO
issued by initiator devices to recipient devices
MICHAEL ALAN;MATHEWSON
BRUCE JAMES;MACE TIMOTHY
CHARLES
ARM;DUBY JEAN2011/12/7 Cascoded level shifter protection
CLAUDE;BLANC FABRICE
Digital data handling in a circuit powered in a high voltage ARM;RIEN MIKAEL;DUBY JEAN2011/12/7 domain and formed from devices designed for operation CLAUDE;GUYONNET
in a lower voltage domain
DAMIEN;PADILLA THIERRY
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2
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2
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0
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386
US8463966B2
2010/10/13
Synchronising activities of various components in a
distributed system
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
387
US8433961B2
2010/5/6
Data processing apparatus and method for testing a
circuit block using scan chains
ARM;HUGHES PAUL STANLEY
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出願日
388
US8429457B2
389
US8427245B2
390
US8427214B2
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US8423752B2
392
US8422262B2
393
US8421821B2
394
US8421516B2
395
US8421513B2
396
US8450954B2
397
US8456199B2
398
US8456223B2
399
US8427198B1
400
US8456140B2
2010/7/14
Power control apparatus and method for controlling a
supply voltage for an associated circuit
401
US8452907B2
2009/9/25
Data processing apparatus and method for arbitrating
access to a shared resource
402
US8463834B2
2009/11/3
Floating point multiplier with first and second partial
product shifting circuitry for result alignment
2009/12/11
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;HARRIS ANTONY
Use of statistical representations of traffic flow in a data
JOHN;CROSSLEY SIMON;BRUCE 登録記録あり
processing system
ALISTAIR CRONE
6
○
登録記録あり
3
○
2010/12/28 Clock state independent retention master-slave flip-flop ARM;PAL SUMANA
登録記録あり
2
○
Apparatus and method for performing permutation
operations in which the ordering of one of a first group
2008/12/16 and a second group of data elements is preserved and
the ordering of the other group of data elements is
changed
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1
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4
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1
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1
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2011/6/2 Ultra low power oscillator
ARM;SANDHU BAL S
2011/4/7 Generating ROM bit cell arrays
2011/12/22 Differential encoding using a 3D graphics processor
2010/2/18
Apparatus and method providing an interface between a
first voltage domain and a second voltage domain
2011/6/1 Master-slave flip-flop circuit
2011/9/19 Electronically controlled universal motor
2010/12/20 Reducing current leakage in a semiconductor device
2011/6/24 Integrated circuit with power gating
2011/12/16 Reduced quantization error I/O resistor calibrator
ARM;SYMES DOMINIC
HUGO;WILDER MLADEN
ARM;NEVERS YANNICK
MARC;SCHUPPE VINCENT
PHILIPPE
ARM NORWAY AS;NYSTAD
JORN;SORGARD
EDVARD;LJOSLAND
BORGAR;BLAZEVIC MARIO
ARM;KUMAR NIDHIR;CHERUKU
SRIDHAR;PRABHU
MANJUNATHA GOVINDA
ARM;PAL SUMANA
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2
○
ARM;PIETROMONACO DAVID V
ARM;YEUNG GUS;GAJJEWAR
HEMANGI UMAKANT
ARM;MYERS JAMES
EDWARD;FLYNN DAVID WALTER
ARM;CHERUKU
SRIDHAR;SUBRAMANIAN
SIVARAMAKRISHNAN;KUMAR
NIDHIR
ARM;PATIL SANJAY
BHAGWAN;FREDERICK JR.
MARLIN WAYNE;GOMEZ
VALENTINA
ARM;RIOCREUX PETER
ANDREW;INGRAM GRAEME
LESLIE
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1
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2
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0
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1
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4
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ARM;LUTZ DAVID RAYMOND
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1
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No.
公報番号
403
US8456214B2
404
US8453073B1
405
US8463960B2
406
US8458532B2
407
US8456939B2
408
US8451039B2
出願日
タイトル (英語)
出願人
State retention circuit and method of operation of such a ARM;FREDERICK JR. MARLIN
2010/11/12
circuit
WAYNE
Method of mask generation for integrated circuit
ARM;DWIVEDI
2012/3/13
fabrication
SHRISAGAR;SAWHNEY PUNEET
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
2011/8/8 Synchronisation of data processing systems
JAMSHED;PRASADH
RAMAMOORTHY GURU;FILIPPO
MICHAEL ALAN
ARM;JAUBERT JOCELYN
Error handling mechanism for a tag memory within
FRANCOIS ORION;BEGON
2010/10/27
coherency control circuitry
FLORENT;TEYSSIER MELANIE
EMANUELLE LUCIE
2010/11/22 Voltage regulation circuitry
ARM;PRABHAT PRANAY
ARM;MYERS JAMES
EDWARD;BIGGS JOHN
2011/5/13 Apparatus for storing a data value in a retention mode
PHILIP;FLYNN DAVID
WALTER;TRADOWSKY CARSTEN
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3
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0
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1
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ARM;BIGGS JOHN PHILIP;MYERS
Integrated circuit, method of generating a layout of an
JAMES EDWARD;HOWARD
2011/5/13 integrated circuit using standard cells, and a standard cell
登録記録あり
DAVID WILLIAM;FLYNN DAVID
library providing such standard cells
WALTER;TRADOWSKY CARSTEN
0
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3
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1
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0
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3
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3
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4
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409
US8451026B2
410
US8418187B2
411
US8418175B2
2009/2/12
412
US8417923B2
2010/6/1
413
US8417920B2
2007/12/21
414
US8417915B2
2005/8/5
415
US8407540B2
2010/6/15
Virtualization software migrating workload between
2010/3/1 processing circuitries while making architectural states
available transparent to operating system
ARM;GREENHALGH PETER
RICHARD;GRISENTHWAITE
RICHARD ROY
ARM;MANSELL DAVID
Data processing apparatus and method for controlling
HENNAH;GRISENTHWAITE
access to secure memory by virtual machines executing
RICHARD ROY;BILES STUART
on processing circuirty
DAVID
ARM;WILLIAMS MICHAEL
Data processing apparatus having trace and prediction
JOHN;HORLEY JOHN
logic
MICHAEL;ASHFIELD EDMOND
JOHN SIMON
ARM;STEVENS ASHLEY
Management of speculative transactions
MILES;CROXFORD DAREN
ARM;GILDAY DAVID
Alias management within a virtually indexed and
MICHAEL;GRISENTHWAITE
physically tagged cache memory
RICHARD ROY
Low overhead circuit and method for predicting timing
ARM;CHANDRA VIKAS
errors
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No.
公報番号
出願日
タイトル (英語)
出願人
Error recover within processing stages of an integrated
circuit
416
US8407537B2
2010/10/13
417
US8407529B2
2011/12/29 Trace synchronization
418
US8407025B2
2009/2/25
419
US8397193B2
2009/4/17 Proprietary circuit layout identification
420
US8395440B2
421
US8395433B2
2010/4/20 Input-output device protection
422
US8390328B2
2011/5/13
423
US8386890B2
2009/9/11 Error correction for multilevel flash memory
2010/11/23
Operating parameter control of an apparatus for
processing data
Apparatus and method for controlling power gating in an
integrated circuit
Supplying a clock signal and a gated clock signal to
synchronous elements
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;FLAUTNER
KRISZTIAN;AUSTIN TODD
MICHAEL;BLAAUW DAVID
THEODORE;MUDGE TREVOR
NIGEL
ARM;HORLEY JOHN
MICHAEL;SWAINE ANDREW
BROOKFIELD;HOULIHANE
THOMAS SEAN;WOODHOUSE
SHELDON JAMES;WILLIAMS
MICHAEL JOHN
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;BLAAUW DAVID
THEODORE;SYLVESTER DENNIS
MICHAEL;FICK DAVID
ALAN;BILES STUART
DAVID;WIECKOWSKI MICHAEL
JOHN;HANSON SCOTT
MCLEAN;CHEN GREGORY
KENGHO
ARM;TING ALBERT LI MING;SU
SHUN-PIAO
ARM;SANDHU BAL S.;IDGUNJI
SATCHIN SATISH;FLYNN DAVID
WALTER
ARM;RIEN MIKAEL;DUBY JEANCLAUDE
ARM;MYERS JAMES
EDWARD;FLYNN DAVID
WALTER;AITKEN ROBERT
CAMPBELL;FREDERICK JR.
MARLIN WAYNE
ARM;WEZELENBURG MARTINUS
CORNELIS;CONWAY THOMAS
KELSHAW
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5
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No.
公報番号
424
US8386754B2
425
US8381162B2
426
US8381083B2
427
US8378861B2
428
US8375196B2
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;BLASCO ALLUE
CONRADO;WILLIAMSON DAVID
Renaming wide register source operand with plural short
JAMES;HARDAGE JAMES
2009/6/24 register source operands for select instructions to detect
登録記録あり
NOLAN;HARRIS GLEN
dependency fast with existing mechanism
ANDREW;MCDONALD ROBERT
GREGORY
Method of adapting a layout of a standard cell of an
2010/10/5
ARM;PELLOIE JEAN-LUC
登録記録あり
integrated circuit
ARM;WEZELENBURG MARTINUS
Error control coding for single error correction and
2009/10/22
登録記録あり
CORNELIS;CONWAY THOMAS
double error detection
KELSHAW
2010/11/29
Storage of probability values for contexts used in
arithmetic coding
Vector processor with vector register file configured as
matrix of data cells each selecting input from generated
2010/1/19
vector data or data from other cell via predetermined
rearrangement path
429
US8375170B2
2010/2/12 Apparatus and method for handling data in a cache
430
US8374098B2
2009/11/3 Check data encoding using parallel lane encoders
431
US8355293B2
2010/12/1 Retention voltage generation
432
US8339876B2
433
US8339409B2
434
US8363484B2
435
US8359588B2
436
US8358551B2
437
US8356119B2
438
US8355276B2
439
US8352819B2
2009/11/9 Memory with improved read stability
Tile-based graphics system and method of operation of
2011/2/16
such a system
Memory device and method of controlling a write
2011/3/9
operation within a memory device
2009/11/25 Reducing inter-task latency in a multiprocessor system
Reducing peak currents required for precharging data
2010/12/20
lines in memory devices
Performance by reducing transaction request ordering
2010/4/26
requirements
Controlling voltage levels applied to access devices when
2009/11/20
accessing storage cells in a memory
2009/4/15 State retention using a variable retention voltage
5
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4
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2
○
ARM;BERKEMAN ANDERS;SYMES
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DOMINIC HUGO
0
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ARM;BJöRKLUND
ANDREAS;PERSSON
ERIK;HUGOSSON OLA
1
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0
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4
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1
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登録記録あり
ARM;LAYCOCK CHRISTOPHER
WILLIAM;HARRIS ANTONY
JOHN;MATHEWSON BRUCE
登録記録あり
JAMES;ROSE ANDREW
CHRISTOPHER;GRISENTHWAITE
RICHARD ROY
ARM;WEZELENBURG MARTINUS
登録記録あり
CORNELIS;PENTON ANTONY
JOHN;WONG KEN YI
ARM
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ARM
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1
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ARM
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0
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ARM
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1
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ARM
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2
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ARM
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0
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ARM
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5
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ARM
登録記録あり
0
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ARM
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0
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No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
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9
○
ARM
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0
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ARM
登録記録あり
1
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ARM
登録記録あり
0
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ARM
登録記録あり
0
○
2011/12/2 Monitoring graphics processing
ARM
Data processing apparatus for storing address
2010/7/1
ARM
translations
2008/1/2 Providing secure services to a non-secure application
ARM
Data processing apparatus and method for connection to
2009/10/20
ARM
interconnect circuitry
2011/2/18 Parallel image encoding
ARM
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2
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登録記録あり
2
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登録記録あり
1
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登録記録あり
2
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0
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ARM
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3
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ARM NORWAY AS
登録記録あり
0
○
Circuit and method operable in functional and diagnostic
modes
Control of clock gating
Stress detection within an integrated circuit having
through silicon vias
Personal electronic device with a dual core processor
440
US8352815B2
2006/10/18
441
US8352794B2
2009/11/19
442
US8347728B2
2010/7/7
443
US8347131B2
2010/10/20
444
US8347067B2
445
US8339414B2
446
US8335908B2
447
US8332660B2
448
US8332564B2
449
US8331703B2
450
US8330478B2
451
US8345051B2
452
US8327034B2
ARM NORWAY AS
登録記録あり
1
○
453
US8285767B2
2011/3/7 Apparatus and method for generating a random number
ARM
登録記録あり
6
○
454
US8327118B2
ARM
登録記録あり
0
○
455
US8321861B2
ARM
登録記録あり
0
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456
US8321726B2
ARM
登録記録あり
0
○
457
US8319518B2
ARM
登録記録あり
0
○
458
US8315123B2
2009/7/21 Scheduling control within a data processing system
Non-native program execution across multiple execution
2008/2/20
environments
2008/6/18 Repairing memory arrays
Detecting transitions in circuits during periodic detection
2009/11/19
windows
2010/12/20 Wordline voltage control within a memory
ARM
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2
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459
US8289343B2
2011/12/8 Method of and apparatus for encoding and decoding data ARM NORWAY AS
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5
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460
US8307138B2
2010/7/12
ARM
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8
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461
US8305825B2
ARM
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462
US8301932B2
ARM
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5
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463
US8301856B2
ARM
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2
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464
US8296538B2
ARM
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2
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465
US8291244B2
ARM
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2008/1/23 Instruction pre-decoding of multiple instruction sets
2009/11/3 Operating parameter monitoring circuit and method
2007/11/28 Processing of 3-dimensional graphics
2006/3/10 Microprocessor systems
Apparatus and method for controlling issuing of
transaction requests
2010/8/5 Timing control circuit
2009/11/16 Synchronising between clock domains
Restricting memory areas for an instruction read in
2010/2/16
dependence upon a hardware mode and a security flag
Storing secure mode page table data in secure and non2011/2/14
secure regions of memory
Power management in a data processing device having
2009/1/5
masters and slaves
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No.
公報番号
466
US8291002B2
467
US8285912B2
468
US8283965B2
469
US8275579B2
470
US8271750B2
471
US8271733B2
472
US8271730B2
473
US8260991B2
474
US8255673B2
475
US8255629B2
476
US8255446B2
477
US8250549B2
478
US8250411B2
479
US8250351B2
480
US8250346B2
481
US8250309B2
482
US8239861B2
483
US8266482B2
484
US8219950B2
485
US8193847B2
486
US8218391B2
487
US8234489B2
出願日
タイトル (英語)
2009/6/1 Barrel shifter
Communication infrastructure for a data processing
2009/8/7 apparatus and a method of operation of such a
communication infrastructure
2010/6/30 Voltage level shifter
Communication of a diagnostic signal and a functional
2011/6/14
signal by an integrated circuit
Entry replacement within a data store using entry profile
2008/1/18
data and runtime performance gain data
2009/7/20 Line allocation in multi-level hierarchical data stores
Handling of write access requests to shared memory in a
2007/10/10
data processing apparatus
Data processing apparatus and method for measuring a
2009/9/15
value of a predetermined property of transactions
2008/4/25 Monitoring transactions in a data processing apparatus
Method and apparatus with data storage protocols for
2009/6/22 maintaining consistencies in parallel translation lookaside
buffers
Apparatus and method for performing rearrangement and
2007/11/29
arithmetic operations on data
Variable coherency support when mapping a computer
2007/10/23
program to a data processing apparatus
2008/12/30 Diagnostic context construction and comparison
2008/12/2 Synchronization of two independent reset signals
2009/6/4 Register renaming of a partially updated data granule
2005/1/28 Control of data accesses to a cache in data processing
Software-based unloading and reloading of an inactive
2008/2/7 function to reduce memory usage of a data processing
task performed using a virtual machine
Operating parameter control for integrated circuit signal
2008/6/24
paths
Propagation delay time balancing in chained inverting
2009/3/20
devices
Timing circuit and method of generating an output timing
2010/10/5
signal
2010/7/1 Power control of an integrated circuit memory
Set of system configuration registers having shadow
2009/7/15
register
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ARM
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ARM
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6
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ARM
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ARM
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0
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ARM
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ARM
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No.
公報番号
出願日
488
US8230277B2
2011/4/4
489
US8228745B2
2010/7/14
490
US8219379B2
2004/11/29
491
US8217702B2
2010/4/5
492
US8213461B2
2006/3/29
493
US8199146B2
2011/2/28
494
US8205206B2
2008/5/8
495
US8200948B2
2007/12/4
496
US8200939B2
2008/1/31
497
US8200902B2
2010/6/10
498
US8195886B2
2007/3/16
499
US8219885B2
2009/4/7
500
US8180980B2
2009/5/22
タイトル (英語)
出願人
Storage of data in data stores having some faulty storage
locations
Two stage voltage level shifting
System, method and computer program product for
testing software
Circuitry for processing signals from a higher voltage
domain using devices designed to operate in a lower
voltage domain
Method of designating slots in a transmission frame for
controlling transmission of data over an interconnect
coupling a plurality of master units with a plurality of
slave units
Processing of computer graphics
Data processing apparatus and method for managing
multiple program threads executed by processing
circuitry
Apparatus and method for performing re-arrangement
operations on data
Memory management unit in a microprocessor system
Cache device for coupling to a memory device and a
method of operation of such a cache device
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM
Data processing apparatus and method for implementing
a replacement scheme for entries of a storage unit
Error detecting and correcting mechanism for a register
file
Device emulation support within a host data processing
apparatus
Single event upset error detection within an integrated
circuit
Error recovery within processing stages of an integrated
circuit
Controlling power consumption in a data processing
apparatus
Boosting voltage levels applied to an access control line
when accessing storage cells in a memory
501
US8185812B2
2006/12/11
502
US8185786B2
2010/10/13
503
US8151126B2
2008/12/29
504
US8164964B2
2009/11/30
505
US8190951B2
2009/8/20
506
US8154353B2
2009/11/3 Operating parameter monitor for an integrated circuit
Handling of errors in a data processing apparatus having
a cache storage and a replicated address storage
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ARM
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0
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ARM
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2
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ARM NORWAY AS
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ARM
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9
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ARM
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0
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ARM NORWAY AS
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0
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ARM
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4
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ARM
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8
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ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
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ARM
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3
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11
○
登録記録あり
3
○
ARM
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1
○
ARM
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0
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ARM
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8
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ARM
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2
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ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
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No.
公報番号
出願日
タイトル (英語)
Transferring data values via a data bus or storing data
values using a selectable representation
Correction of single event upset error within sequential
storage circuitry of an integrated circuit
Cache accessing using a micro TAG
Mapping a computer program to an asymmetric
multiprocessing apparatus
Bus interconnect device and a data processing apparatus
including such a bus interconnect device
Apparatus and method for error correction of data values
in a storage device
Interconnect logic for a data processing apparatus
Providing tuning limits for operational parameters in data
processing apparatus
Trace synchronization
Handling of memory access requests to shared memory
in a data processing apparatus
Apparatus and method for tracing activities of a shader
program executed on shader circuitry of a data
processing apparatus
Single event upset error detection within sequential
storage circuitry of an integrated circuit
Monitoring values of signals within an integrated circuit
Apparatus and method for performing hardware and
software co-verification testing
System and method for modelling a hardware component
of a data processing apparatus
Interrupt control for virtual processing apparatus
出願人
審査･権利状況被引用回数外国出願
ARM
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ARM
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8
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ARM
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0
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ARM
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30
○
ARM
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2
○
ARM
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2
○
ARM
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1
○
ARM
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0
○
ARM
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6
○
ARM
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4
○
ARM
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1
○
ARM
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3
○
ARM
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0
○
ARM
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4
○
ARM
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1
○
ARM
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17
○
507
US8171311B2
2009/5/1
508
US8161367B2
2008/10/7
509
US8151055B2
2009/2/25
510
US8190807B2
2007/10/23
511
US8171191B2
2009/1/28
512
US8190973B2
2007/12/21
513
US8190801B2
2006/5/25
514
US8185791B2
2009/5/22
515
US8176366B2
2009/4/3
516
US8176262B2
2009/4/6
517
US8159491B2
2009/12/3
518
US8171386B2
2008/3/27
519
US8185724B2
2008/9/3
520
US8180620B2
2004/1/27
521
US8160861B2
2008/1/14
522
US8131901B2
2009/6/4
523
US8102402B2
2008/6/23 Method of and apparatus for encoding data
ARM NORWAY AS
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9
○
524
US8112560B2
2010/8/24 Controlling complex non-linear data transfers
ARM
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0
○
525
US8144167B2
ARM
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0
○
526
US8103990B2
ARM
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1
○
527
US8145960B2
登録記録あり
3
○
528
US8134824B2
2009/7/16 Monitoring graphics processing
Characterising circuit cell performance variability in
2008/2/28 response to perturbations in manufacturing process
parameters
Storage of data in data stores having some faulty storage
2007/7/2
locations
2008/2/19 Decoupling capacitors
登録記録あり
1
○
529
US8131942B2
2008/4/17 Control data modification within a cache memory
ARM
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ARM
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
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No.
公報番号
出願日
タイトル (英語)
Debugging a multiprocessor system that switches
2010/1/21
between a locked mode and a split mode
Data processing apparatus and method for handling
2008/5/21 address translation for access requests issued by
processing circuitry
2008/11/3 Standard cell placement
出願人
審査･権利状況被引用回数外国出願
ARM
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0
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ARM
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9
○
ARM
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9
○
ARM
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2
○
ARM
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6
○
ARM
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0
○
ARM NORWAY AS
登録記録あり
2
○
ARM
登録記録あり
14
○
ARM
登録記録あり
2
○
ARM
登録記録あり
11
○
530
US8108730B2
531
US8140820B2
532
US8136072B2
533
US8103918B2
534
US8145844B2
535
US8122232B2
536
US8115783B2
537
US8112681B2
538
US8132254B2
539
US8145958B2
540
US8106921B2
ARM NORWAY AS
登録記録あり
8
○
541
US8108596B2
2009/1/29 Memory controller address mapping scheme
ARM
登録記録あり
5
○
542
US8116165B2
2010/4/21 Memory with improved data reliability
登録記録あり
0
○
543
US8103922B2
2011/6/16 Error detection in precharged logic
ARM
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
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0
○
544
US8059144B2
2010/3/3
ARM
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1
○
545
US8060814B2
2009/8/21
登録記録あり
4
○
546
US8067971B2
2009/9/18
登録記録あり
2
○
547
US8099635B2
2010/10/6
ARM
登録記録あり
0
○
548
US8099556B2
2008/2/13
ARM
登録記録あり
2
○
549
US8093938B2
ARM
登録記録あり
4
○
550
US8086883B2
ARM
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4
○
551
US8086829B2
ARM
登録記録あり
2
○
552
US8082589B2
ARM
登録記録あり
5
○
2008/3/25 Clock control during self-test of multi port memory
Memory controller with write data cache and read data
2007/12/13
cache
2007/6/21 Self programming slave device controller
Methods of and apparatus for processing computer
2008/1/31
graphics
Method and apparatus for handling fuse data for repairing
2008/1/29
faulty elements within an IC
Protecting system control registers in a data processing
2007/8/15
apparatus
Integrated circuit and method for testing memory on the
2005/11/10
integrated circuit
2007/1/30 Differential encoding using a 3d graphics processor
Generating and resolving pixel values within a graphics
processing pipeline
Error recovery within processing stages of an integrated
circuit
Providing additional inputs to a latch circuit
Techniques for generating a trace stream for a data
processing apparatus
Cache miss detection in a data processing apparatus
2010/4/20 Cascoded level shifter protection
Hardware driven processor state storage prior to
2008/11/5
entering a low power
Method and apparatus for processing data related to
2009/3/5
handling interrupts in data processing
Diagnostic data capture control for multi-domain
2003/11/17
processors
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Error recovery following speculative execution with an
instruction processing pipeline
Modifying integrated circuit layout
Result path sharing between a plurality of execution units
within a processor
Initialisation of a pipelined processor
Compensating for non-uniform boundary conditions in
standard cells
Cache management within a data processing apparatus
出願人
審査･権利状況被引用回数外国出願
ARM
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1
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ARM
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5
○
ARM
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0
○
ARM
登録記録あり
2
○
ARM
登録記録あり
1
○
553
US8037287B2
2008/3/14
554
US8051400B2
2008/10/21
555
US8051275B2
2009/6/1
556
US8055888B2
2008/2/28
557
US8051390B2
2008/10/7
558
US8041897B2
2008/7/24
ARM
登録記録あり
11
○
559
US8015337B2
2009/3/23 Power efficient interrupt detection
ARM
登録記録あり
6
○
560
US8045402B2
2009/6/29 Assisting write operations to data storage cells
ARM
登録記録あり
8
○
561
US8045401B2
ARM
登録記録あり
0
○
562
US8055872B2
ARM
登録記録あり
2
○
563
US8051323B2
ARM
登録記録あり
5
○
564
US8041930B2
ARM
登録記録あり
0
○
565
US8014226B2
ARM
登録記録あり
0
○
566
US8055883B2
ARM
登録記録あり
0
○
567
US8051401B2
ARM
登録記録あり
1
○
568
US8051271B2
ARM
登録記録あり
0
○
569
US8050114B2
ARM
登録記録あり
2
○
570
US8045573B2
ARM
登録記録あり
0
○
571
US8024690B2
ARM
登録記録あり
3
○
572
US8055950B2
ARM
登録記録あり
7
○
573
US8044971B2
ARM NORWAY AS
登録記録あり
7
○
2009/9/18 Supporting scan functions within memories
Data processor with hardware accelerator, accelerator
2008/2/21
interface and shared memory management unit
Auxiliary circuit structure in a split-lock dual processor
2010/1/21
system
Data processing apparatus and method for controlling
2007/11/1 thread access of register sets when selectively operating
in secure and non-secure domains
Integrated circuit memory with word line driving helper
2009/12/22
circuits
Pipe scheduling for pipelines based on destination
2009/7/1
register number
Post-routing power supply modification for an integrated
2008/10/15
circuit
2008/7/1 Translation of virtual to physical addresses
Memory device having a single pass-gate transistor per
2008/10/14 bitline column multiplexer coupled to latch circuitry and
method thereof
Bit ordering for packetised serial data transmission on an
2009/6/1
integrated circuit
Method, system and computer program product for
determining routing of data paths in interconnect
2008/5/19 circuitry providing a narrow interface for connection to a
first device and a wide interface for connection to a
distributed plurality of further devices
Method and apparatus for improved timing for trace
2008/1/11
synchronization
Methods of and apparatus for processing computer
2008/1/31
graphics
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
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2
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ARM
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0
○
ARM
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1
○
ARM
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7
○
ARM
登録記録あり
2
○
ARM
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2
○
ARM
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0
○
ARM
登録記録あり
6
○
ARM
登録記録あり
7
○
ARM
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0
○
ARM
登録記録あり
3
○
ARM
登録記録あり
2
○
2007/11/5 Dynamically changing control of sequenced power gating ARM
登録記録あり
3
○
ARM
登録記録あり
2
○
ARM
登録記録あり
4
○
ARM
登録記録あり
6
○
ARM
登録記録あり
5
○
Generation of trace elements within a data processing
apparatus
Data processing apparatus and method for instruction
pre-decoding
Communication of a diagnostic signal and a functional
signal by an integrated circuit
Recovering from errors in streaming DSP applications
Data processing apparatus and method for performing a
reciprocal operation on an input value to produce a result
value
Data processing apparatus and method for performing
floating point multiplication
Distributing power to an integrated circuit
574
US8037363B2
2008/12/29
575
US8037286B2
2008/1/23
576
US8036854B2
2007/11/20
577
US8020039B2
2008/12/1
578
US8015228B2
2005/2/16
579
US8015231B2
2004/11/30
580
US7986504B2
2009/6/3
581
US8010772B2
582
US7987407B2
583
US8006147B2
584
US8004913B2
585
US8010774B2
586
US7977822B2
587
US8000156B2
588
US8001331B2
589
US7979642B2
590
US8001428B2
591
US7991960B2
2008/8/27 Adaptive comparison control in a data store
ARM
登録記録あり
6
○
592
US7984269B2
Data processing apparatus and method for reducing issue
circuitry responsibility by using a predetermined pipeline
2007/6/12
ARM
stage to schedule a next operation in a sequence of
operations defined by a complex instruction
登録記録あり
0
○
593
US7979822B2
登録記録あり
4
○
2008/2/6 Protected function calling
Handling of hard errors in a cache of a data processing
2009/8/20
apparatus
2009/3/16 Error detection in precharged logic
Redundancy architecture for an integrated circuit
2010/5/20
memory
Breakpointing on register access events or I/O port
2006/11/3
access events
Memory device with propagation circuitry in each subarray and method thereof
2008/4/17 Efficiency of cache memory operations
Managing the storage of high-priority storage items in
2008/9/11 storage units in multi-core and multi-threaded systems
using history storage and control circuitry
2008/10/27 Packing trace protocols within trace streams
2008/10/24
Apparatus and method for performing a sequence of
2008/6/3 verification tests to verify a design of a data processing
system
ARM
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Diagnosing faults within programs being executed by
virtual machines
Apparatus and method for data processing having an onchip or off-chip interconnect between two or more
devices
Memory testing
Data processing apparatus and method for handling
interrupts
Data processing apparatus and method for converting a
number between fixed-point and floating-point
representations
Techniques for generating a trace stream for a data
processing apparatus
Generating ROM bit cell arrays
Integrated circuit layout pattern for cross-coupled
circuits
Diagnostic mode switching
出願人
審査･権利状況被引用回数外国出願
ARM
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ARM
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ARM
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8
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ARM
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6
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ARM
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ARM
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ARM
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ARM
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ARM
594
US8010849B2
2006/9/7
595
US8006008B2
2007/8/21
596
US8006144B2
2007/6/7
597
US8010726B2
2004/3/1
598
US7945607B2
2007/5/15
599
US7937626B2
2008/2/26
600
US7961490B2
2009/1/9
601
US7960759B2
2008/10/14
602
US7949914B2
2010/1/29
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0
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603
US7949866B2
2009/3/20 Exception types within a secure processing system
ARM
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8
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604
US7948816B2
2009/3/24 Accessing data within a memory formed of memory banks ARM
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ARM
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1
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605
US7941584B2
606
US7940546B2
607
US7924056B2
608
US7949848B2
609
US7945806B2
610
US7937535B2
611
US7934029B2
612
US7925871B2
613
US7925836B2
614
US7936578B2
615
US7936290B2
Data processing apparatus and method for performing
2009/3/26
hazard detection
2009/1/30 ROM array
ARM
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6
○
2009/5/26 Low voltage differential signalling driver
Data processing apparatus, method and computer
2007/3/8 program product for reducing memory usage of an object
oriented program
Data processing apparatus and method for controlling a
2007/10/25
transfer of payload data over a communication channel
Managing cache coherency in a data processing
2007/2/22
apparatus
Data transfer between devices within an integrated
2009/2/3
circuit
Identification and correction of cyclically recurring errors
2008/2/19
in one or more branch predictors
2008/1/25 Selective coherency control
ARM
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3
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ARM
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7
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ARM
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0
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ARM
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11
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ARM
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0
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ARM
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0
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ARM
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0
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2009/8/28 Read only memory cell for storing a multiple bit value
Dynamic selection of suitable codes for variable length
2009/11/2
coding and decoding
ARM
登録記録あり
3
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ARM
登録記録あり
0
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Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
616
US7945811B2
2008/10/2
617
US7925867B2
2009/7/14
618
US7925866B2
2008/12/3
619
US7925840B2
2008/9/5
620
US7966466B2
2008/2/6
621
US7962664B2
2008/9/26
622
US7941608B2
2009/3/17
623
US7926021B2
2007/9/25
624
US7925868B2
2007/1/24
625
US7924638B2
2007/4/18
626
US7958335B2
2005/8/5
627
US7924858B2
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
Low power, high reliability specific compound functional
units
Pre-decode checking for pre-decoded instructions that
cross cache line boundaries
Data processing apparatus and method for handling
instructions to be executed by processing circuitry
Data processing apparatus and method for managing
snoop operations
Memory domain based security control with data
processing systems
Techniques for generating a trace stream for a data
processing apparatus
Cache eviction
Insertion of error detection circuits based on error
propagation within integrated circuits
Suppressing register renaming for conditional instructions
predicted as not executed
Redundancy architecture for an integrated circuit
memory
Multiple instruction set decoding
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
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0
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ARM
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ARM
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1
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ARM
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1
○
ARM
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12
○
ARM
登録記録あり
5
○
ARM
登録記録あり
0
○
ARM
登録記録あり
2
○
ARM
登録記録あり
16
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ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
ARM
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0
○
ARM
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5
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ARM
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0
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ARM
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8
○
ARM
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0
○
ARM
登録記録あり
4
○
ARM NORWAY AS
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9
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ARM
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6
○
ARM
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0
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ARM
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3
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ARM;TEXAS INSTRUMENTS
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4
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2006/4/13 Use of a data engine within a data processing apparatus
Data processing apparatus and method for controlling
access to memory
Compare and branch mechanism
Power control circuitry, circuitry for analysing a switched
power rail, and method of controlling connection of a
power source to a switched power rail
Data access target predictions in a data processing
system
Cache circuitry, data processing apparatus and method
for prefetching data by selecting one of a first prefetch
linefill operation and a second prefetch linefill operation
Processing of computer graphics
628
US7949835B2
2005/9/21
629
US7930526B2
2004/3/24
630
US7898278B2
2007/11/5
631
US7900019B2
2006/5/1
632
US7917701B2
2007/3/12
633
US7920139B2
2007/5/29
634
US7920411B2
635
US7895417B2
636
US7913120B2
637
US7900020B2
2009/2/25 Converting SRAM cells to ROM cells
Select-and-insert instruction within data processing
2010/4/30
systems
Selective disabling of diagnostic functions within a data
2008/2/11
processing system
2008/1/25 Correction of incorrect cache accesses
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
638
US7893722B2
639
US7917735B2
640
US7913131B2
641
US7895469B2
642
US7886098B2
2007/9/13 Memory access security management
643
US7920584B2
2006/4/12 Data processing system
644
US7882293B2
645
US7873757B2
646
US7843760B2
647
US7839016B2
648
US7859937B2
649
US7873896B2
650
US7870437B2
651
US7876634B2
652
US7865675B2
653
US7863778B2
654
US7856532B2
655
US7844800B2
656
US7849296B2
657
US7877587B2
658
US7855924B2
659
US7836320B2
660
US7866560B2
661
US7840001B2
662
US7861095B2
2008/9/11 Clock control of state storage circuitry
ARM
Data processing apparatus and method for pre-decoding
2008/1/23
ARM
instructions
2008/1/7 Scan chain cell with delay testing capability
ARM
審査･権利状況被引用回数外国出願
登録記録あり
2
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登録記録あり
2
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登録記録あり
7
○
ARM
登録記録あり
8
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ARM
登録記録あり
9
○
ARM
登録記録あり
9
○
ARM
登録記録あり
12
○
2007/2/16 Controlling complex non-linear data transfers
Interface circuit and method for coupling between a
2009/3/16
memory device and processing circuitry
Maintaining output I/O signals within an integrated circuit
2007/12/13
with multiple power domains
Apparatus and method for controlling write access to a
2009/1/12
group of storage elements
2008/10/1 High performance pulsed storage circuit
ARM
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0
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ARM
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1
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ARM
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5
○
ARM
登録記録あり
0
○
ARM
登録記録あり
2
○
2007/11/14 Trace data timestamping
Apparatus and method for adjusting a supply voltage
2008/6/2
based on a read result
Controlling cleaning of data values within a hardware
2007/12/6
accelerator
2007/11/14 Power controlling integrated circuit cell
Cache logic, data processing apparatus including cache
2006/11/3
logic, and a method of operating cache logic
Method for renaming a large number of registers in a data
2007/8/21
processing system using a background channel
Monitoring control for monitoring at least two domains of
2003/11/17
multi-domain processors
2006/6/9 Branch prediction within a multithreaded processor
Data processing memory circuit having pull-down circuit
2006/5/19
with on/off configuration
Power management in a data processing apparatus
2006/7/7 having a plurality of domains in which devices of the data
processing apparatus can operate
Recovering communication transaction control between
2007/1/4
independent domains of an integrated circuit
2005/11/4 Data processing apparatus
ARM
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6
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ARM
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2
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ARM
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1
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ARM
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6
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ARM
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6
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ARM
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0
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ARM
登録記録あり
4
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ARM
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4
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ARM
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0
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ARM
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13
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ARM
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1
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ARM
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1
○
ARM
登録記録あり
6
○
2008/10/14 Integrated circuit using speculative execution
2004/7/9 Interrupt masking control
2005/2/15 Data processing apparatus security
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
663
US7836288B2
2004/9/14
664
US7863733B2
2008/1/10
665
US7856346B2
2002/5/10
666
US7849310B2
2003/11/17
667
US7805595B2
2007/4/20
668
US7831815B2
2008/2/6
669
US7822926B2
2007/4/16
670
US7814302B2
2008/2/13
671
US7788417B2
2007/7/2
672
US7823019B2
673
US7802040B2
674
US7793181B2
675
US7809972B2
676
US7809930B2
677
US7808273B2
678
US7805645B2
679
US7809989B2
680
US7793082B2
681
US7830176B2
682
US7797681B2
683
US7822884B2
684
US7814297B2
685
US7797520B2
686
US7797518B2
タイトル (英語)
Branch prediction mechanism including a branch
prediction memory and a branch prediction cache
Integrated circuit with multiple layers of circuits
Emulating multiple bus used within a data processing
system
Switching between secure and non-secure processing
modes
Data processing apparatus and method for updating
prediction data based on an operation's priority level
Data processing apparatus and method for identifying
sequences of instructions
Cache memory
Address calculation instruction within data processing
systems
Target device programmer
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
0
○
ARM
登録記録あり
3
○
ARM
登録記録あり
3
○
ARM
登録記録あり
32
○
ARM
登録記録あり
13
○
ARM
登録記録あり
6
○
ARM
登録記録あり
17
○
ARM
登録記録あり
0
○
ARM
登録記録あり
1
○
2008/5/8 Debug circuitry
Arbitration method reordering transactions to ensure
2008/6/9
quality of service specified by each transaction
2008/3/27 Sequential storage circuitry for an integrated circuit
Data processing apparatus and method for translating a
2007/3/30 signal between a first clock domain and a second clock
domain
2007/1/24 Selective suppression of register renaming
ARM
登録記録あり
2
○
ARM
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16
○
ARM
登録記録あり
3
○
ARM
登録記録あり
3
○
ARM
登録記録あり
1
○
2008/2/20 Reducing leakage power in low power mode
Data processing apparatus and method for testing
2008/1/11
stability of memory cells in a memory device
Performing diagnostic operations upon an asymmetric
2007/10/18
multiprocessor apparatus
2006/12/14 Latch to block short path violation
Controlling signal levels on a signal line within an
2006/7/27
integrated circuit
Stack memory selection upon exception in a data
2006/5/11
processing system
Distributed direct memory access provision within a data
2006/12/12
processing system
2005/7/26 Algebraic single instruction multiple data processing
ARM
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3
○
ARM
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4
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ARM
登録記録あり
1
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ARM
登録記録あり
4
○
ARM
登録記録あり
1
○
ARM
登録記録あり
1
○
ARM
登録記録あり
0
○
ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
ARM
登録記録あり
0
○
2005/6/30 Early branch instruction prediction
Generating instruction sets for compacting long
2005/9/8
instructions
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
687
US7805557B2
688
US7793078B2
689
US7822947B2
690
US7805550B2
691
US7831806B2
692
US7802080B2
693
US7788472B2
694
US7831817B2
695
US7822955B2
696
US7743238B2
697
US7757027B2
698
US7769936B2
2008/3/5
699
US7752425B2
2006/5/30
700
US7770078B2
2008/5/23
701
US7745275B2
2008/9/10
702
US7769982B2
2007/8/15
703
US7769955B2
2007/4/27
704
US7752424B2
2007/8/8
705
US7747839B2
2008/1/23
706
US7783869B2
2006/12/19
707
US7743294B2
2006/11/20
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
5
○
ARM
登録記録あり
0
○
ARM
登録記録あり
2
○
ARM
登録記録あり
11
○
ARM
登録記録あり
2
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
8
○
ARM
登録記録あり
15
○
ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
Data processing apparatus and method for arbitrating
ARM
between messages routed over a communication channel
登録記録あり
11
○
ARM
登録記録あり
2
○
ARM
登録記録あり
1
○
ARM
登録記録あり
2
○
ARM
登録記録あり
2
○
ARM
登録記録あり
13
○
ARM
登録記録あり
0
○
ARM
登録記録あり
2
○
ARM
登録記録あり
2
○
ARM
登録記録あり
1
○
2005/7/12 Interrupt controller and method for handling interrupts
Multiple instruction set data processing system with
conditional branch instructions of a first instruction set
2005/4/1
and a second instruction set sharing a same instruction
encoding
2004/7/13 Aliasing data processing registers
Management of polling loops in a data processing
2005/1/11
apparatus
Determining target addresses for instruction flow
2004/2/18
changing instructions in a data processing apparatus
2004/3/24 Null exception handling
Instruction encoding within a data processing apparatus
2004/2/20
having multiple instruction sets
2003/4/15 Two-level branch prediction apparatus
Data processing apparatus and method for utilizing
2003/1/21
endianess independent data values
Accessing items of architectural state from a register
cache in a data processing apparatus when performing
2003/5/9
branch prediction operations for an indirect branch
instruction
Control of master/slave communication within an
2008/6/19
integrated circuit
Data processing apparatus having trace and prediction
logic
Integrated circuit communication self-testing
Integrated circuit and a method of making an integrated
circuit to provide a gate contact over a diffusion region
Data processing apparatus and method for accelerating
execution of subgraphs
Multiple thread instruction fetch from different cache
levels
Null value checking instruction
Data processing apparatus and method for handling
instructions to be executed by processing circuitry
Accessing branch predictions ahead of instruction
fetching
Diagnostic mode switching
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
708
US7743366B2
ARM
登録記録あり
3
○
709
US7774582B2
ARM
登録記録あり
0
○
710
US7761665B2
ARM
登録記録あり
3
○
711
US7747667B2
ARM
登録記録あり
1
○
712
US7761280B2
ARM
登録記録あり
0
○
713
US7761693B2
ARM
登録記録あり
3
○
714
US7751642B1
ARM
登録記録あり
13
○
715
US7698534B2
ARM
登録記録あり
1
○
716
US7734853B2
ARM
登録記録あり
4
○
717
US7729185B2
ARM
登録記録あり
8
○
718
US7723867B2
ARM
登録記録あり
10
○
719
US7698537B2
ARM
登録記録あり
2
○
720
US7737720B2
ARM
登録記録あり
36
○
721
US7734974B2
2007/7/11 Serial scan chain control within an integrated circuit
722
US7711882B2
ARM
登録記録あり
6
○
2008/10/9 Interrupt jitter suppression
ARM
Instruction issue control within a multi-threaded in-order
2007/4/25
ARM
superscalar processor
2007/8/13 Power control circuitry and method
ARM
登録記録あり
0
○
723
US7707390B2
登録記録あり
4
○
724
US7696649B2
725
US7706172B2
726
US7707394B2
727
US7734897B2
728
US7730545B2
2005/10/3 System and method for compiling a computer program
Result bypassing to override a data hazard within a
2005/5/26
superscalar processor
Handling of cache accesses in a data processing
2005/5/23
apparatus
Data processing apparatus and method for determining
2005/2/16 an initial estimate of a result value of a reciprocal
operation
Data processing apparatus simulation by generating
2004/3/17
anticipated timing information for bus data transfers
Data processing apparatus and method for performing
2004/7/13
arithmetic operations in SIMD data processing
Methods and devices for image processing, image
2006/5/17
capturing and image downscaling
Reordering application code to improve processing
2007/2/21
performance
2008/4/11 Latency dependent data bus transmission
Apparatus and method for detection of address decoder
2007/12/14
open faults
2007/5/30 Power gating of circuits
Data processing apparatus for processing a stream of
instructions in first and second processing blocks with
2006/12/20 the first processing block supporting register renaming
and the second processing block not supporting register
renaming
2007/5/3 Virtual power rail modulation within an integrated circuit
2007/8/27 Layout of a SRAM memory cell
Reducing the size of a data stream produced during
2006/5/30
instruction tracing
Allocation of memory access operations to memory
access capable pipelines in a superscalar data processing
2005/12/21
apparatus and method having a plurality of execution
threads
2005/5/23 Test access control for secure integrated circuits
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14
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ARM
登録記録あり
2
○
ARM
登録記録あり
46
○
ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
729
公報番号
US7725695B2
出願日
2005/5/31
タイトル (英語)
Branch prediction apparatus for repurposing a branch to
instruction set as a non-predicted branch
Integrated circuit with error correction mechanisms to
offset narrow tolerancing
Error detection and recovery within processing stages of
an integrated circuit
Control of metastability in the pipelined data processing
apparatus
Task following between multiple operating systems
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
0
○
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
登録記録あり
4
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
21
○
ARM
登録記録あり
2
○
730
US7701240B2
2005/12/13
731
US7650551B2
2007/8/16
732
US7653795B2
2008/2/8
733
US7661104B2
2003/11/17
ARM
登録記録あり
33
○
734
US7688668B2
登録記録あり
4
○
735
US7673187B2
2007/11/28 Controlling power supply to memory cells
ARM
Data processing apparatus and method for reducing trace
2006/10/24
ARM
bandwidth
登録記録あり
1
○
736
US7657694B2
2006/12/20 Handling access requests in a data processing apparatus ARM
登録記録あり
3
○
ARM
登録記録あり
5
○
ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
ARM
登録記録あり
0
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
0
○
ARM
登録記録あり
1
○
ARM
登録記録あり
7
○
ARM
登録記録あり
1
○
ARM
登録記録あり
3
○
ARM
登録記録あり
50
○
ARM
登録記録あり
24
○
2003/6/16 Result partitioning within SIMD data processing systems ARM
登録記録あり
1
○
ARM
登録記録あり
0
○
ARM
登録記録あり
14
○
ARM
登録記録あり
22
○
737
US7664901B2
2007/3/27
738
US7660186B2
2007/10/17
739
US7650483B2
2006/11/3
740
US7650479B2
2006/9/20
741
US7685404B2
2007/6/5
742
US7689735B2
743
US7668892B2
744
US7657587B2
745
US7650524B2
746
US7668896B2
747
US7689811B2
748
US7668897B2
749
US7676652B2
750
US7661105B2
751
US7647480B2
Data processing apparatus and method for arbitrating
access to a shared resource
Memory clock generator having multiple clock modes
Execution of instructions within a data processing
apparatus having a plurality of processing units
Maintaining cache coherency for secure and non-secure
data access requests
Program subgraph identification
2005/10/3 Instruction stream control
Data processing apparatus and method for normalizing a
2005/8/25
data value
2005/8/11 Multi-dimensional fast fourier transform
Circuit and modes for storing data in operational and
2006/3/22
sleep modes
Data processing apparatus and method for performing
2005/3/17
floating point multiplication
Method and apparatus for constant generation in SIMD
2004/7/13
processing
Executing variable length instructions stored within a
2003/8/27
plurality of discrete memory address regions
2003/11/17 Exception types within a secure processing system
Handling of conditional instructions in a data processing
2007/1/18
apparatus
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
752
US7624253B2
753
US7613053B2
754
US7613052B2
755
US7624215B2
756
US7616041B2
757
US7606108B2
758
US7605644B2
759
US7640397B2
760
US7603605B2
761
US7617409B2
762
US7606057B2
763
US7603496B2
764
US7630388B2
765
出願日
タイトル (英語)
2006/10/25 Determining register availability for register renaming
Memory device and method of operating such a memory
2007/11/23
device
Memory device and method of operating such a memory
2007/11/1
device
2008/1/24 Interrupt controller
2008/9/19 Data retention in operational and sleep modes
2007/11/16 Access collision within a multiport memory
Integrated circuit power-on control and programmable
2007/5/3
comparator
2006/10/11 Adaptive comparison control in a memory
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
12
○
ARM
登録記録あり
1
○
ARM
登録記録あり
12
○
ARM
登録記録あり
41
○
ARM
登録記録あり
11
○
ARM
登録記録あり
1
○
ARM
登録記録あり
12
○
ARM
登録記録あり
2
○
2007/1/8 Performance control of an integrated circuit
ARM
登録記録あり
6
○
2006/5/1 System for checking clock-signal correspondence
ARM
登録記録あり
16
○
ARM
登録記録あり
3
○
ARM
登録記録あり
3
○
ARM
登録記録あり
1
○
US7627807B2
2005/4/26 Monitoring a data processor to detect abnormal operation ARM
登録記録あり
0
○
766
US7644399B2
2004/12/3
ARM
登録記録あり
2
○
767
US7640286B2
2005/3/11
ARM
登録記録あり
3
○
768
US7647489B2
2005/3/14
ARM
登録記録あり
2
○
769
US7613911B2
2004/3/12
ARM
登録記録あり
0
○
770
US7607133B2
2004/2/11
ARM
登録記録あり
1
○
771
US7647368B2
2004/9/1
ARM
登録記録あり
0
○
772
US7627462B2
2001/11/27
ARM
登録記録あり
3
○
773
US7558895B2
ARM
登録記録あり
11
○
774
US7596663B2
Identifying a cache way of a cache access request using
ARM
information from the microtag and from the micro TLB
登録記録あり
2
○
2006/5/31 Metal line layout in a memory cell
Buffering data during data transfer through a plurality of
2006/1/23
channels
Software defined FIFO memory for storing a set of data
2005/5/4
from a stream of source data
Forming an executable program from a list of program
instructions
Data processing apparatus and method for performing
floating point multiplication
Function calling mechanism with embedded index for a
handler program and an embedded immediate value for
passing a parameter
Prefetching exception vectors by early lookup exception
vectors within a cache memory
Interrupt processing control
Data processing apparatus and method for performing
data processing operations on floating point data
elements
Hardware simulation using a test scenario manager
2007/7/30 Interconnect logic for a data processing apparatus
2006/11/15
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Word reordering upon bus size resizing to reduce
Hamming distance
Generation of trace elements within a data processing
apparatus
Reusing a buffer memory as a microcache for program
instructions of a detected program loop
Power saving in memory arrays
Cache circuitry, data processing apparatus and method
for handling write access requests
Speculative data value usage
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
4
○
ARM
登録記録あり
6
○
ARM
登録記録あり
12
○
ARM
登録記録あり
4
○
ARM
登録記録あり
2
○
ARM
登録記録あり
16
○
775
US7565516B2
2006/2/28
776
US7562258B2
2006/2/9
777
US7571305B2
2007/1/11
778
US7558104B2
2007/2/5
779
US7600077B2
2007/1/10
780
US7590826B2
2006/11/6
781
US7574314B2
2007/9/17 Spurious signal detection
ARM
登録記録あり
3
○
782
US7568072B2
ARM
登録記録あり
3
○
783
US7587556B2
ARM
登録記録あり
0
○
784
US7558938B2
2006/8/31 Cache eviction
Store buffer capable of maintaining associated cache
2006/3/29
information
2006/2/8 Memory bus encoding
ARM
登録記録あり
2
○
785
US7587444B2
ARM
登録記録あり
2
○
786
US7599974B2
ARM
登録記録あり
3
○
787
US7599998B2
ARM
登録記録あり
4
○
788
US7600141B2
ARM
登録記録あり
13
○
789
US7539853B2
ARM
登録記録あり
11
○
790
US7533241B2
ARM
登録記録あり
1
○
791
US7533226B2
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
12
○
792
US7529916B2
ARM
登録記録あり
15
○
793
US7529889B2
ARM
登録記録あり
6
○
794
US7523420B2
ARM
登録記録あり
0
○
Efficient use of co-processor in platform independent
instruction machine by controlling result transfer and
2006/12/19
ARM
translation and transfer timing of subsequent instruction
based on instruction type for result forwarding
登録記録あり
2
○
登録記録あり
10
○
795
US7516302B2
796
US7514975B2
2005/4/26 Data value addition
Data processing apparatus and method for comparing
2004/3/22
floating point operands
Message handling communication between a source
2004/7/7
processor core and destination processor cores
2003/11/19 Data processing performance control
Handling interrupts in data processing of data in which
2003/11/17
only a portion of a function has been processed
Variable size cache memory support within an integrated
2006/12/6
circuit
2006/2/14 Data processor memory circuit
Data processing apparatus and method for controlling
2006/8/16
access to registers
Data processing apparatus and method for performing a
2006/8/14
cache lookup in an energy efficient manner
2006/8/18 Degeneration technique for designing memory devices
2006/5/2 Data retention in operational and sleep modes
ARM
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
797
US7512820B2
2006/9/13
798
US7509502B2
2004/9/1
799
US7508836B2
2004/12/1
800
US7506091B2
801
US7552363B2
802
US7552285B2
803
US7546642B2
804
US7549024B2
805
US7549059B2
806
US7496899B2
807
US7496813B1
808
US7495976B2
809
US7490221B2
810
811
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
Performance level selection in a data processing system
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
by combining a plurality of performance requests
9
○
Data processing apparatus and method for merging
secure and non-secure data into an output data stream
ARM
登録記録あり
5
○
Data processing apparatus and method for handling
transactions
ARM
登録記録あり
1
○
2006/11/22 Interrupt controller utilising programmable priority values ARM
登録記録あり
12
○
ARM
登録記録あり
0
○
Generation of trace elements within a data processing
2006/3/23
apparatus
2006/8/30 Line fill techniques
ARM
登録記録あり
2
○
ARM
登録記録あり
3
○
ARM
登録記録あり
9
○
ARM
登録記録あり
0
○
ARM
登録記録あり
0
○
ARM
登録記録あり
8
○
ARM
登録記録あり
4
○
ARM
登録記録あり
15
○
US7490030B2
2004/7/9 Latching processor state information
Multi-processing system with coherent and non2004/7/1
coherent modes
Transferring data values via a data bus or storing data
2002/6/26
values using a selectable representation
Preventing loss of traced information in a data
2005/8/17
processing apparatus
Communicating simultaneously a functional signal and a
2005/11/30 diagnostic signal for an integrated circuit using a shared
pin
2007/1/8 Repairing integrated circuit memory arrays
Synchronization between pipelines in a data processing
2003/6/24
apparatus utilizing a synchronization queue
2002/11/4 Power modelling of a circuit
ARM
登録記録あり
9
○
US7489752B2
2005/12/22 Synchronisation of signals between asynchronous logic
ARM
登録記録あり
0
○
812
US7489178B2
2006/12/28 Level shifter for use between voltage domains
ARM
登録記録あり
6
○
813
US7487367B2
2003/11/17 Apparatus and method for managing access to a memory ARM
登録記録あり
34
○
814
US7484069B2
2006/9/28 Watchpointing unaligned data accesses
ARM
登録記録あり
2
○
815
US7475394B2
2003/12/5 System and method of analyzing interpreted programs
ARM
登録記録あり
10
○
816
US7472225B2
2005/6/20 Caching data
ARM
登録記録あり
3
○
817
US7426629B2
2005/3/15 Processing activity masking in a data processing system ARM
登録記録あり
24
○
818
US7449922B1
2007/6/15
登録記録あり
30
○
Sensing circuitry and method of detecting a change in
voltage on at least one input line
ARM
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Data processing system having an external instruction
2003/7/1
set and an internal instruction set
Allocation of branch target cache resources in
2006/8/10 dependence upon program instructions within an
instruction queue
Handling multiple interrupts in a data processing system
2003/11/17
utilising multiple operating systems
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
7
○
ARM
登録記録あり
7
○
ARM
登録記録あり
3
○
登録記録あり
13
○
ARM
登録記録あり
0
○
ARM
登録記録あり
11
○
ARM
登録記録あり
1
○
819
US7406585B2
820
US7447883B2
821
US7448050B2
822
US7447946B2
2004/11/5 Storage of trace data within a data processing apparatus ARM
823
US7447885B2
2005/4/20
824
US7447882B2
825
US7447871B2
826
US7447726B2
ARM
登録記録あり
6
○
827
US7447099B2
2005/12/15 Leakage mitigation logic
ARM
登録記録あり
2
○
828
US7444546B2
ARM
登録記録あり
42
○
829
US7444271B2
ARM
登録記録あり
2
○
830
US7444257B2
ARM
登録記録あり
6
○
831
US7437544B2
ARM
登録記録あり
0
○
832
US7437400B2
ARM
登録記録あり
5
○
833
US7434119B2
2003/4/17 On-board diagnostic circuit for an integrated circuit
Scoring mechanism for automatically generated test
2004/12/3
programs
Generation of a testbench for a representation of a
2003/12/23
device
Data processing apparatus and method for executing a
2005/4/29 sequence of instructions including a multiple iteration
instruction
Data processing apparatus and method for performing
2005/3/14
floating point addition
2005/3/7 Method and apparatus for memory self testing
ARM
登録記録あり
0
○
834
US7434072B2
ARM
登録記録あり
19
○
835
US7434007B2
ARM
登録記録あり
5
○
836
US7433911B2
ARM
登録記録あり
2
○
837
US7428632B2
ARM
登録記録あり
0
○
838
US7426659B2
ARM
登録記録あり
2
○
839
US7426320B2
2005/4/25 Integrated circuit power management control
Management of cache memories in a data processing
2005/3/29
apparatus
Data processing apparatus and method for performing
2004/12/21
floating point addition
Branch prediction mechanism using a branch cache
2005/3/24
memory and an extended pattern cache
2005/3/22 Forced diagnostic entry upon power-up
Performance controlling parameter setting in an image
2004/5/7
processing system
ARM
登録記録あり
7
○
840
US7420970B2
2003/6/16 Read ports and methods of outputting data via read ports ARM
登録記録あり
0
○
Reading prediction outcomes within a branch prediction
mechanism
Context switching within a data processing system
2005/4/20
having a branch prediction mechanism
2007/2/7 Data access program instruction encoding
2004/6/3 Polynomial and integer multiplication
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
5
○
ARM
登録記録あり
23
○
ARM
登録記録あり
4
○
ARM
登録記録あり
2
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
26
○
ARM
登録記録あり
4
○
ARM
登録記録あり
2
○
ARM
登録記録あり
0
○
ARM
登録記録あり
3
○
ARM
登録記録あり
1
○
2003/11/17 Exception handling control in a secure processing system ARM
登録記録あり
18
○
ARM
登録記録あり
6
○
ARM
登録記録あり
40
○
ARM
登録記録あり
3
○
Memory device and method of controlling access to such
a memory device
Communication interface for diagnostic circuits of an
integrated circuit
Controlling execution of a block of program instructions
within a computer processing system
Memory device and method for performing write
operations in such a memory device
Recovery from errors in a data processing apparatus
Compiling computer programs to exploit parallelism
without exceeding available processing resources
Selecting subroutine return mechanisms
Data processing apparatus and method for converting a
fixed point number to a floating point number
Provision of debug via a separate ring bus in a data
processing apparatus
Data processing apparatus and method for computing an
absolute difference between first and second data
elements
841
US7420859B2
2006/12/7
842
US7412633B2
2006/1/31
843
US7386709B2
2004/1/13
844
US7379347B1
2006/11/30
845
US7401273B2
2005/2/4
846
US7401329B2
2005/4/25
847
US7401210B2
2005/3/30
848
US7401107B2
2004/12/22
849
US7389459B2
2005/3/22
850
US7386580B2
2004/3/18
851
US7383587B2
852
US7373550B2
853
US7370210B2
854
US7370180B2
855
US7366650B2
2002/2/22 Software and hardware simulation
ARM
登録記録あり
13
○
856
US7363176B2
2005/12/6 Operating voltage determination for an integrated circuit ARM
登録記録あり
37
○
857
US7360061B2
2004/12/6
登録記録あり
0
○
858
US7356553B2
登録記録あり
1
○
859
US7313677B2
2005/3/14 Processing activity masking in a data processing system ARM
登録記録あり
19
○
860
US7350055B2
12
○
861
US7337356B2
34
○
862
US7320091B2
2005/1/31 Tightly coupled accelerator
ARM
登録記録あり
Systematic and random error detection and recovery
2004/7/23
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
within processing stages of an integrated circuit
Error recovery within processing stages of an integrated
2005/4/21
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
circuit
42
○
Generation of a computer program to test for correct
operation of a data processing apparatus
Apparatus and method for managing processor
2003/11/17
configuration data
2004/3/8 Bit field extraction with sign or zero extend
2005/2/3
Program instruction decompression and compression
ARM
techniques
Data processing apparatus and method for determining a
2004/3/18 processing path to perform a data processing operation ARM
on input data elements
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
863
US7310755B2
2004/2/18 Data retention latch provision within integrated circuits
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
24
○
864
US7339842B1
2006/8/16 Timing control for sense amplifiers in a memory circuit
ARM
登録記録あり
2
○
865
US7305712B2
ARM
登録記録あり
19
○
866
US7328295B2
ARM
登録記録あり
9
○
867
US7324368B2
ARM
登録記録あり
20
○
868
US7353297B2
ARM
登録記録あり
0
○
869
US7350058B2
ARM
登録記録あり
4
○
870
US7350005B2
2003/11/17 Security mode switching via an exception vector
Interrupt controller and interrupt controlling method for
2003/12/18 prioritizing interrupt requests generated by a plurality of
interrupt sources
2006/3/30 Integrated circuit memory with write assist
Handling of write transactions in a data processing
2004/6/8
apparatus
Shift and insert instruction for overwriting a subset of
2004/8/30 data within a register with a shifted result of another
register
Handling interrupts in a system having multiple data
2003/5/23
processing units
ARM
登録記録あり
12
○
871
US7330994B2
2005/4/26 Clock control of a multiple clock domain data processor
ARM
登録記録あり
11
○
872
US7315796B2
ARM
登録記録あり
3
○
873
US7308623B2
ARM
登録記録あり
8
○
874
US7343482B2
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
18
○
875
US7343481B2
2006/5/10 Data processing performance control
Integrated circuit and method for testing memory on the
2005/3/10
integrated circuit
2005/1/31 Program subgraph identification
Branch prediction in a data processing system utilizing a
2003/3/19
cache of previous static predictions
ARM
登録記録あり
4
○
876
US7330798B2
2006/4/18 Operating voltage determination for an integrated circuit ARM
登録記録あり
2
○
登録記録あり
47
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
3
○
ARM
登録記録あり
68
○
ARM
登録記録あり
8
○
ARM
登録記録あり
9
○
ARM
登録記録あり
16
○
ARM
登録記録あり
8
○
ARM
登録記録あり
15
○
877
US7340573B2
2003/11/17
878
US7318143B2
2005/1/28
879
US7334161B2
2004/4/30
880
US7315600B2
2004/3/30
881
US7308631B2
2002/9/13
882
US7328391B2
883
US7325168B2
884
US7325083B2
タイトル (英語)
出願人
Apparatus and method for controlling access to a
memory unit
Reuseable configuration data
Breakpoint logic unit, debug logic and breakpoint method
for a data processing apparatus
Asynchronous FIFO apparatus and method for passing
data between a first clock domain and a second clock
domain and a second clock domain of a data processing
apparatus
Wrapper serial scan chain functional segmentation
2004/7/1 Error correction within a cache memory
Trace data source identification within a trace data
2003/11/19
stream
Delivering data processing requests to a suspended
2003/11/17
operating system
ARM
Copyright 2016 Innovation Research Corporation
審査･権利状況被引用回数外国出願
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
885
US7321942B2
886
US7315875B2
887
US7305534B2
888
US7289373B1
889
US7278073B2
890
US7293212B2
891
US7290075B2
892
US7278080B2
893
US7260694B2
894
US7263015B2
895
US7260001B2
896
US7262631B2
897
US7302552B2
898
US7254667B2
899
US7254658B2
900
US7269759B2
901
US7283930B2
902
US7269766B2
903
US7260711B2
904
US7219215B2
905
US7206982B1
906
US7236995B2
出願日
2003/10/20
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
Performance counter for adding variable work increment
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
value that is dependent upon clock frequency
2004/1/27 Data filtering
22
○
ARM
登録記録あり
0
○
ARM
登録記録あり
56
○
ARM
登録記録あり
8
○
2003/4/17 Diagnostic data capture within an integrated circuit
ARM
Memory self-test via a ring bus in a data processing
2005/3/22
ARM LIMTED
apparatus
2006/5/11 Performing arbitration in a data processing apparatus
ARM
Error detection and recovery within processing stages of
2003/3/20
ARM;UNIVERSITY OF MICHIGAN
an integrated circuit
2006/9/26 Data processor memory circuit
ARM;UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
2005/11/7 Address decoding
UNIVERSITY OF MICHIGAN
Memory system having fast and slow data reading
2006/5/30
ARM
mechanisms
2005/4/11 Method and apparatus for controlling a voltage level
ARM
System for processing VLIW words containing variable
2004/10/14 length instructions having embedded instruction length
ARM
identifiers
Data transfer between an external data source and a
2004/4/2
ARM
memory associated with a data processor
2004/6/8 Write transaction interleaving
ARM
Data processing apparatus and method for handling
2004/8/6
ARM
corrupted data values
2003/11/19 Data processing performance control
ARM
登録記録あり
20
○
登録記録あり
5
○
登録記録あり
2
○
登録記録あり
44
○
登録記録あり
8
○
登録記録あり
4
○
登録記録あり
7
○
登録記録あり
17
○
登録記録あり
18
○
登録記録あり
4
○
登録記録あり
2
○
登録記録あり
16
○
登録記録あり
21
○
2001/12/26 Method and apparatus for memory self testing
Single instruction multiple data processing allowing the
2001/9/24 combination of portions of two data words with a single
pack instruction
Data processing apparatus and method for moving data
2004/7/13 elements between specified registers and a continuous
block of memory
2004/6/16 Diagnostic mechanism for an integrated circuit
Data processing apparatus and method for converting a
2002/12/27 number between fixed-point and floating-point
representations
ARM
登録記録あり
13
○
ARM
登録記録あり
7
○
ARM
登録記録あり
17
○
ARM
登録記録あり
12
○
ARM
登録記録あり
21
○
2003/11/17 Control of access to a memory by a device
2006/6/6 High performance memory device
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
907
US7248508B1
908
US7234043B2
909
US7219178B2
910
US7249270B2
911
US7240144B2
912
US7221205B2
913
US7213095B2
914
US7213092B2
915
US7228457B2
916
US7206884B2
917
US7243206B2
918
US7240268B2
919
US7231507B2
920
US7219214B2
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
4
○
ARM
登録記録あり
7
○
ARM
登録記録あり
27
○
Method and apparatus for placing at least one processor
into a power saving mode when another processor has
2005/1/28 access to a shared resource and exiting the power saving ARM
mode upon notification that the shared resource is no
longer required by the other processor
登録記録あり
33
○
ARM
登録記録あり
4
○
ARM
登録記録あり
15
○
ARM
登録記録あり
9
○
ARM
登録記録あり
0
○
ARM
登録記録あり
4
○
2004/2/11 Interrupt priority control within a nested interrupt system ARM
登録記録あり
5
○
登録記録あり
4
○
登録記録あり
7
○
登録記録あり
1
○
登録記録あり
4
○
登録記録あり
3
○
ARM
登録記録あり
4
○
ARM
登録記録あり
16
○
ARM
登録記録あり
17
○
ARM
登録記録あり
10
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
38
○
2006/1/11 Data retention in a semiconductor memory
Decoding predication instructions within a superscaler
2005/3/7
data processing system
2004/9/30 Bus deadlock avoidance
2004/4/2 Arbitration of data transfer requests
Circuit and method for storing data in operational,
2004/7/6
diagnostic and sleep modes
Bus transaction management within data processing
2004/6/8
systems
2004/6/8 Write response signalling within a communication bus
Performing diagnostic operations upon a data processing
2004/3/16
apparatus with power down support
Method and apparatus for using a RAM memory block to
2003/4/14
ARM
remap ROM access requests
2003/5/30 Test component and method of operation thereof
ARM
2004/1/28 Data access program instruction encoding
ARM
Data processing apparatus and method for moving data
2004/7/13 elements between a chosen lane of parallel processing in ARM
registers and a structure within memory
921
US7210023B2
Data processing apparatus and method for moving data
between registers and memory in response to an access
2004/7/13
ARM
instruction having an alignment specifier identifying an
alignment to be associated with a start address
922
US7251751B2
2004/3/16 Diagnostic mechanisms within multi processing systems
923
US7231476B2
924
US7228543B2
925
US7216332B2
926
US7162661B2
2003/11/17 Function control for a processor
Technique for reaching consistent state in a multi2003/1/24
threaded data processing system
2003/3/5 Software object library selection
Systematic and random error detection and recovery
2004/2/18
within processing stages of an integrated circuit
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Technique for accessing memory in a data processing
apparatus
Circuit and method for storing data in operational and
sleep modes
Latch circuit including a data retention latch
Communication transaction control between independent
domains of an integrated circuit
Recovering pending trace data within a data processing
system
Transaction request servicing mechanism
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
28
○
ARM
登録記録あり
18
○
ARM
登録記録あり
12
○
ARM
登録記録あり
5
○
ARM
登録記録あり
0
○
ARM
登録記録あり
33
○
927
US7185159B2
2003/11/17
928
US7180348B2
2005/3/24
929
US7154317B2
2005/1/11
930
US7165729B2
2005/1/31
931
US7191293B2
2004/3/16
932
US7181556B2
2003/12/23
933
US7178011B2
2004/1/29 Predication instruction within a data processing system
ARM
登録記録あり
32
○
934
US7174472B2
2003/5/20 Low overhead integrated circuit power down and restart
ARM
登録記録あり
10
○
935
US7162590B2
ARM
登録記録あり
67
○
936
US7152186B2
ARM
登録記録あり
26
○
937
US7197680B2
ARM
登録記録あり
23
○
938
US7197671B2
ARM
登録記録あり
9
○
939
US7194647B2
ARM
登録記録あり
6
○
940
US7194385B2
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
26
○
941
US7181633B2
ARM
登録記録あり
1
○
942
US7171539B2
ARM
登録記録あり
66
○
943
US7162611B2
ARM
登録記録あり
4
○
944
US7134003B2
ARM
登録記録あり
10
○
945
US7146491B2
ARM
登録記録あり
0
○
946
US7143221B2
ARM
登録記録あり
10
○
947
US7124261B2
ARM
登録記録あり
5
○
Memory bus within a coherent multi-processing system
2004/3/1 having a main portion and a coherent multi-processing
portion
2003/8/4 Cross-triggering of processing devices
Communication interface for diagnostic circuits of an
2003/4/17
integrated circuit
Generation of trace elements within a data processing
2003/6/3
apparatus
2003/11/19 Data processing performance control
2003/10/20 Performance level setting of a data processing system
Data processing performance control based on a status
2003/11/19 signal indicating the maximum voltage that can be
supported
Apparatus and method for controlling access to a
2003/11/17
memory
Unhandled operation handling in multiple instruction set
2002/5/2
systems
Variable cycle instruction execution in variable or
2004/11/12
maximum fixed cycle mode to disguise execution path
2004/10/26 Apparatus and method for generating constant values
Method of arbitrating between a plurality of transfers to
be routed over a corresponding plurality of paths
2004/6/8
provided by an interconnect circuit of a data processing
apparatus
Access to bit values within data words stored in a
2004/2/9
memory
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
Vectored interrupt control within a system having a
2003/11/17
ARM
secure domain and a non-secure domain
Data processing apparatus and method for performing in
2004/7/13
ARM
parallel a data processing operation on data elements
2003/8/7 Data processing system trace bus
ARM
948
US7117284B2
949
US7145480B2
950
US7149933B2
951
US7149862B2
2004/9/3 Access control in a data processing apparatus
ARM
952
US7142996B2
2004/8/6 Operating voltage determination for an integrated circuit ARM
953
US7134031B2
954
US7120779B2
955
US7117277B2
956
US7111126B2
957
US7134119B2
958
US7134117B2
959
US7131118B2
960
US7131015B2
961
US7124274B2
2003/11/17
962
US7110934B2
2002/10/29
963
US7107585B2
964
US7068545B1
965
US7076392B1
966
US7072229B2
967
US7085874B2
968
US7080178B2
969
US7069376B2
審査･権利状況被引用回数外国出願
登録記録あり
57
○
登録記録あり
6
○
登録記録あり
13
○
登録記録あり
41
○
登録記録あり
20
○
ARM
登録記録あり
61
○
ARM
登録記録あり
4
○
ARM
登録記録あり
15
○
ARM
登録記録あり
4
○
ARM
登録記録あり
24
○
ARM
登録記録あり
13
○
ARM
登録記録あり
0
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
31
○
登録記録あり
40
○
ARM.
登録記録あり
7
○
ARM
登録記録あり
19
○
2005/1/4 Data processing apparatus having memory protection unit ARM
登録記録あり
24
○
ARM
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
登録記録あり
12
○
登録記録あり
0
○
ARM
登録記録あり
8
○
ARM
登録記録あり
5
○
ARM
登録記録あり
33
○
2003/8/4 Performance control within a multi-processor system
Address offset generation within a data processing
2004/1/28
system
Flexibility of design of a bus interconnect block for a data
2004/5/18
processing apparatus
2003/9/24 Apparatus and method for loading data values
Intercalling between native and non-native instruction
2001/6/25
sets
2003/1/28 Instruction tracing in data processing systems
Write-through caching a JAVA® local variable within a
2002/7/25
register of a register bank
Performance level selection in a data processing system
2003/10/20 using a plurality of performance request calculating
algorithms
Virtual to physical memory address mapping within a
ARM
system having a secure domain and a non-secure domain
Analysis of the performance of a portion of a data
processing system
Compilation of application code in a data processing
2002/7/29
apparatus
2000/10/6 Test bit-stream generator and method for decoders
Memory system having fast and slow data reading
2005/6/13
mechanisms
Synchronous/asynchronous bridge circuit for improved
2004/4/2
transfer of data between two circuits
Interrupt pre-emption and ordering within a data
2004/2/9
processing system
2004/5/18 Flexibility of use of a data processing apparatus
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
970
US7069176B2
971
US7053675B2
972
US7099813B2
973
US7093236B2
974
US7093108B2
975
US7089539B2
976
US7089393B2
977
US7089174B2
978
US7085978B2
979
US7080299B2
980
US7080289B2
981
US7076771B2
982
US7062689B2
983
US7055007B2
984
US7005910B2
985
US7005913B2
986
US7005889B2
987
US7002258B2
988
US7050958B1
989
US7047401B2
990
US7031337B2
991
US7024543B2
992
US7020768B2
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
46
○
2003/7/25 Switching between clocks in data processing
Simulating program instruction execution and hardware
2002/4/9
device operation
2001/2/1 Tracing out-of-order data
Apparatus and method for efficiently incorporating
2001/6/8
instruction set information with instruction addresses
2002/2/25 Program instruction interpretation
ARM
登録記録あり
3
○
ARM
登録記録あり
3
○
ARM
登録記録あり
45
○
ARM
登録記録あり
16
○
ARM
登録記録あり
19
○
2002/1/11 Data processing using a coprocessor
Modelling device behaviour using a first model, a second
2003/2/21
model and stored valid behaviour
Validating test signal connections within an integrated
2002/9/17
circuit
Resetting latch circuits within a functional circuit and a
2003/2/3
test wrapper circuit
2001/10/10 Tracing multiple data access instructions
ARM
登録記録あり
3
○
ARM
登録記録あり
7
○
ARM
登録記録あり
6
○
ARM
登録記録あり
16
○
ARM
登録記録あり
71
○
2000/12/1 Instruction interpretation within a data processing system ARM
登録記録あり
2
○
登録記録あり
39
○
2003/4/10 Data processor memory circuit
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
Feed-forward circuit for reducing delay through an input
2004/1/16
ARM PHYSICAL IP
登録記録あり
buffer
2004/3/22 I/O buffer with wide range voltage translator
ARM PHYSICAL IP
登録記録あり
42
○
6
○
4
○
2004/7/9 Level shifting in a data processing apparatus
Dual port memory core cell architecture with matched bit
2003/12/3
line capacitances
Method and apparatus for accelerating hardware
2000/6/2
simulation
Handling interrupts during multiple access program
2003/6/16
instructions
Data processing apparatus and slave interface
2001/5/1 mechanism for controlling access to a slave logic unit by
a plurality of master logic units
2002/9/13 Synchronising pipelines in a data processing apparatus
Apparatus and method for facilitating debugging of
2001/2/26 sequences of processing instructions using context
identifier comparison
2003/8/7 Trace source correlation in a data processing apparatus
2001/12/20 Method and apparatus for memory self testing
ARM
ARM
登録記録あり
17
○
ARM PHYSICAL IP
登録記録あり
14
○
ARM
登録記録あり
23
○
ARM
登録記録あり
12
○
ARM
登録記録あり
1
○
ARM
登録記録あり
1
○
ARM
登録記録あり
17
○
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
出願人
993
US7020751B2
Write back cache memory control within data processing
2002/7/25
ARM
system
994
US7017030B2
2002/2/20 Prediction of instructions in a data processing apparatus ARM
995
US7016930B2
2002/10/25
996
US7016370B2
2001/1/16
997
US7003699B2
2002/7/29
998
US7003652B2
2001/6/25
999
US6959351B2
2003/4/3
1000
1001
1002
1003
1004
1005
1006
US6993469B1
US6950951B2
US6999900B2
US6999354B2
US6999985B2
US6958718B2
US7000094B2
2000/6/2
2002/4/30
2004/3/30
2004/4/27
2001/8/30
2004/7/13
2001/6/25
1007
US6990569B2
2001/10/25
1008
US6981131B2
2002/9/4
1009
US6978358B2
2002/4/2
1010
1011
1012
1013
US6976126B2
US6965984B2
US6954828B2
US6952761B2
2003/3/11
2002/4/30
2003/8/7
2002/10/22
1014
US6895056B2
2002/1/30
1015
US6944067B2
2004/2/18
1016
US6904517B2
2001/11/2
1017
US6941442B2
2002/8/2
1018
US6918103B2
2001/10/26
Apparatus and method for performing operations
implemented by iterative execution of a recurrence
equation
Controller and method for controlling interfacing to a
data link
Generation of trace signals within a data processing
apparatus
Restarting translated instructions
Handling of a multi-access instruction in a data
processing apparatus
Method and apparatus for unified simulation
Power control signalling
Testing memory access signal connections
Dynamically adaptable memory
Single instruction multiple data processing
Table lookup operation within a data processing system
Storing stack operands in registers
Handling problematic events in a data processing
apparatus
Early condition code evaluation at pipeline stages
generating pass signals for controlling coprocessor
pipeline executing same conditional instruction
Executing stack-based instructions within a data
processing apparatus arranged to apply operations to
data items stored in registers
Accessing data values in a cache
Data processing using multiple instruction sets
Management of caches in a data processing apparatus
Bus interface selection by page table attributes
Data processing apparatus and method for performing an
adaptive filter operation on an input data sample
Memory system having fast and slow data reading
mechanisms
Data processing apparatus and method for saving return
state
Entry lockdown within a translation lookaside buffer
mechanism
Integrated circuit configuration
審査･権利状況被引用回数外国出願
登録記録あり
24
○
登録記録あり
12
○
ARM
登録記録あり
4
○
ARM
登録記録あり
2
○
ARM
登録記録あり
25
○
ARM
登録記録あり
24
○
ARM
登録記録あり
10
○
ARM
ARM
ARM
ARM PHYSICAL IP
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
登録記録あり
登録記録あり
登録記録あり
登録記録あり
51
5
1
1
8
27
8
○
○
○
○
○
○
○
ARM
登録記録あり
5
○
ARM
登録記録あり
19
○
ARM
登録記録あり
17
○
ARM
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
登録記録あり
42
28
1
26
○
○
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ARM
登録記録あり
5
○
ARM
登録記録あり
18
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ARM
登録記録あり
17
○
ARM
登録記録あり
13
○
ARM
登録記録あり
20
○
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
36
○
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
11
0
8
○
○
○
ARM
登録記録あり
16
○
ARM
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8
○
ARM
ARM
登録記録あり
登録記録あり
74
6
○
○
2002/10/1 Memory access prediction in a data processing apparatus ARM
登録記録あり
9
○
ARM
登録記録あり
3
○
ARM
登録記録あり
11
○
ARM
ARM
登録記録あり
登録記録あり
19
0
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○
ARM
登録記録あり
53
○
ARM
登録記録あり
6
○
ARM
登録記録あり
20
○
ARM
登録記録あり
4
○
ARM
登録記録あり
15
○
ARM
登録記録あり
6
○
ARM
登録記録あり
10
○
ARM
登録記録あり
16
○
ARM
登録記録あり
0
○
ARM
登録記録あり
6
○
ARM
登録記録あり
29
○
ARM
登録記録あり
7
○
1019
US6910206B1
2000/11/7
1020
1021
1022
US6907515B2
US6904500B2
US6892257B2
2002/5/22
2002/7/30
2001/12/5
1023
US6883102B2
2001/12/18
1024
US6883085B2
2002/7/25
1025
1026
US6876941B2
US6853968B2
2002/2/28
2000/12/20
1027
US6851033B2
1028
US6842849B2
1029
US6795841B2
1030
1031
US6826670B2
US6816943B2
1032
US6789098B1
1033
US6831952B2
1034
US6785179B1
1035
US6760798B1
1036
US6782452B2
1037
US6742012B2
1038
US6779143B2
1039
US6701427B1
1040
US6721861B2
1041
US6708317B2
1042
US6691270B2
1043
US6687771B2
タイトル (英語)
Data processing with native and interpreted program
instruction words
Configuration control within data processing systems
Cache controller
Exclusive access control to a processing resource
Apparatus and method for performing power management
functions
Handling of coprocessor instructions in a data processing
apparatus
Testing compliance of a device with a bus protocol
Simulation of data processing apparatus
2001/5/21 Locking source registers in a data processing apparatus
Parallel processing of multiple data values within a data
2001/1/29
word
2002/5/31 Accessing memory units in a data processing apparatus
2003/5/6 Scratch pad memories
Method, data processing system and computer program
2000/10/23
for comparing floating point numbers
System, method and computer program for decoding an
2001/3/7
encoded data stream
Charge sharing between bit lines within a memory circuit
2003/6/19
to increase recharge speed
Interface mechanism and method for interfacing a real2000/7/13
time clock with a data processing circuit
Apparatus and method for processing data using a
2001/12/11 merging cache line fill to allow access to cache entries
before a line fill is completed
Apparatus and method for performing multiplication
2000/12/27
operations
Asynchronous testing of reset operation in an integrated
2001/7/5
circuit
Data processing apparatus and method for processing
1999/12/22
floating point instructions
Indicator of validity status information for data storage
2002/12/30
within a data processing system
2001/12/21 Validating integrated circuits
Integrated circuit and method of operation of such a
2000/12/22
circuit employing serial test scan chains
Parallel processing of multiple data values within a data
2001/1/26
word
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
タイトル (英語)
Bus arbitration circuit responsive to latency of access
requests and the state of the memory circuit
Management of caches in a data processing apparatus
Scratch pad memories
Zero result prediction
Branch searching to prioritize received interrupt signals
Asynchronously accessing the program counter values of
a data processing system by applying an independent
clock on the latching and scan-chain circuits
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
33
○
ARM
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
登録記録あり
6
8
16
13
○
○
○
○
1044
US6684302B2
2002/7/25
1045
1046
1047
1048
US6671779B2
US6643736B1
US6629118B1
US6584532B1
2001/9/20
2000/8/29
1999/12/7
2000/5/17
1049
US6598150B2
2001/10/3
ARM
登録記録あり
10
○
1050
US6598061B1
2000/6/15 System and method for performing modular multiplication ARM
登録記録あり
23
○
1051
1052
US6564301B1
US6552949B1
ARM
ARM
登録記録あり
登録記録あり
37
26
○
○
1053
US6550005B1
ARM
登録記録あり
4
○
1054
US6542916B1
ARM
登録記録あり
29
○
1055
US6532553B1
ARM
登録記録あり
22
○
1056
US6513053B1
ARM
登録記録あり
7
○
1057
US6504495B1
ARM
登録記録あり
6
○
1058
US6490655B1
ARM
登録記録あり
58
○
1059
US6463488B1
ARM
登録記録あり
62
○
1060
US6411957B1
ARM
登録記録あり
67
○
1061
1062
US6446221B1
US6424179B1
ARM
ARM
登録記録あり
登録記録あり
52
4
○
○
1063
US6418491B1
ARM
登録記録あり
5
○
1064
US6415365B1
ARM
登録記録あり
9
○
1065
US6411958B1
ARM
登録記録あり
4
○
1066
US6366978B1
ARM
登録記録あり
32
○
1067
US6360189B1
ARM
登録記録あり
59
○
1068
US6353879B1
1999/2/19 Memory address translation in a data processing system ARM
登録記録あり
7
○
1999/7/6 Management of caches in a data processing apparatus
2002/2/5 Reducing leakage current in a memory device
Mechanism for recovery from termination of a program
1999/11/29 instruction due to an exception in a pipeland processing
system
Data processing apparatus and method for applying
1999/7/28 floating-point operations to first, second and third
operands
1999/9/29 Debugging data processing systems
Data processing circuit and method for determining the
2000/1/12 first and subsequent occurences of a predetermined
value in a sequence of data bits
1999/2/17 Clipping data values in a data processing system
Data processing apparatus and method for cache line
1999/9/13 replacement responsive to the operational state of
memory
Apparatus and method for testing master logic units
1999/6/14
within a data processing apparatus
System and method of organizing nodes within a tree
1999/6/30
structure
1999/5/19 Debug mechanism for data processing systems
2001/2/21 Logic unit and integrated circuit for clearing interrupts
Apparatus and method for controlling timing of transfer
1999/6/25
requests within a data processing apparatus
2001/11/29 Write buffer for use in a data processing apparatus
Data processing system and method for generating a
1999/3/1
structured listing of symbols
1999/11/5 Cache memory
Data processing apparatus and method for performing
1998/8/31
multiply-accumulate operations
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
1069
1070
US6345335B1
US6343358B1
1071
US6338135B1
1072
1073
US6289417B1
US6332186B1
1074
US6314443B1
1075
出願日
タイトル (英語)
1999/9/13 Data processing memory system
1999/5/19 Executing multiple debug instructions
Data processing system and method for performing an
1998/11/20
arithmetic operation on a plurality of signed data values
1998/5/18 Operand supply to an execution unit
1998/8/28 Vector register addressing
Double/saturate/add/saturate and
1998/11/20 double/saturate/subtract/saturate operations in a data
processing system
出願人
審査･権利状況被引用回数外国出願
ARM
ARM
登録記録あり
登録記録あり
ARM
ARM
ARM
5
48
○
○
登録記録あり
2
○
登録記録あり
登録記録あり
13
36
○
○
ARM
登録記録あり
16
○
US6304198B1
2000/9/28 Bitmap font data storage within data processing systems ARM
登録記録あり
1
○
1076
US6282634B1
1998/5/27
ARM
登録記録あり
30
○
1077
US6321329B1
ARM
登録記録あり
92
○
1078
US6304963B1
ARM
登録記録あり
24
○
1079
US6272033B1
ARM
登録記録あり
20
○
1080
US6236342B1
1999/5/6 Bitmap font data storage within data processing systems ARM
登録記録あり
7
○
1081
US6278334B1
1999/11/29
ARM
登録記録あり
7
○
1082
US6259459B1
1998/7/1
ARM
登録記録あり
101
○
1083
1084
1085
US6247113B1
US6189094B1
US6218879B1
1998/5/27
1998/5/27
1999/3/12
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
117
61
8
○
○
○
1086
US6216222B1
1998/5/14
ARM
登録記録あり
18
○
1087
US6172530B1
1999/6/18
ARM
登録記録あり
6
○
1088
US6170001B1
1998/5/27
ARM
登録記録あり
39
○
1089
1090
1091
1092
US6148314A
US6140843A
US6115729A
US6108682A
1998/8/28
1998/8/20
1998/8/20
1998/5/14
ARM
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
登録記録あり
15
9
20
34
○
○
○
○
1093
US6101573A
1998/6/12
ARM
登録記録あり
8
○
1094
US6043698A
1997/11/3
ARM
登録記録あり
47
○
Apparatus and method for processing data having a
mixed vector/scalar register file
1999/5/19 Executing debug instructions
Handling exceptions occuring during processing of vector
1998/8/31
instructions
2000/2/24 Status bits for cache memory
Voltage controlled oscillator with accelerating and
decelerating circuits
Apparatus and method for image data processing of pixel
data in raster lines
Coprocessor opcode division by data type
Recirculating register file
S-R flip-flop circuit
Handling exceptions in a pipelined data processing
apparatus
Decoder for generating N output signals from two or
more precharged input signals
System for transfering format data from format register
to memory wherein format data indicating the distribution
of single or double precision data type in the register
bank
Round increment in an adder circuit
Conditional invert functions in precharged circuits
Floating point multiply-accumulate unit
Division and/or square root calculating circuit
Bit line and/or match line partitioned content
addressable memory
Voltage level shifter
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
外国出願あり（各国）
No.
公報番号
出願日
1095
US6021476A
1997/9/2
1096
US6058439A
1997/3/31
1097
US6035383A
1997/11/3
1098
US6069611A
1997/3/28
1099
US6064626A
1998/7/31
1100
US6052774A
1998/3/6
1101
1102
US6034545A
US6021265A
1998/1/30
1997/4/14
1103
US6018794A
1997/4/30
1104
1105
1106
US6002881A
US5969975A
US5917771A
1997/9/17
1996/10/8
1997/11/3
1107
US5918058A
1997/2/20
1108
US5961631A
1997/7/16
1109
US5935197A
1997/3/21
1110
1111
1112
1113
1114
US5961633A
US5960186A
US5951630A
US5918042A
US5905684A
1996/3/22
1997/8/4
1997/1/10
1997/1/10
1997/11/3
1115
US5881263A
1996/10/8
1116
US5881259A
1996/10/8
1117
US5881257A
1996/10/8
1118
US5875465A
1997/4/3
1119
US5809037A
1997/1/9
タイトル (英語)
Data processing apparatus and method for controlling
access to a memory having a plurality of memory
locations for storing data values
Asynchronous first-in-first-out buffer circuit burst mode
control
Memory access request result prediction prior to confirm
signal generation
Display palette programming utilizing frames of data
which also contain color palette updating data to prevent
display distortion or sparkle
Peripheral buses for integrated circuit
Apparatus and method for identifying exception routines
indicated by instruction address issued with an
instruction fetch command
Macrocell for data processing circuit
Interoperability with multiple instruction sets
Data processing apparatus and method for generating
timing signals for a self-timed circuit
Coprocessor data access control
Data processing apparatus registers
Register bank bit lines
Routing of clock signals in a data processing circuit with
a power saving mode of operation
Data processing apparatus and method for pre-fetching
an instruction in to an instruction cache
Data processing circuit and method of operation
performing arithmetic processing on data signals
Execution of data processing instructions
Digital circuit simulation with data interface scheduling
Digital adder circuit
Dynamic logic pipeline control
Memory bit line output buffer
Non-instruction base register addressing in a data
processing apparatus
Input operand size and hi/low word selection control in
data processing systems
Data processing system register control
Cache control circuit having a pseudo random address
generator
Integrated circuit testing
出願人
審査･権利状況被引用回数外国出願
ARM
登録記録あり
32
○
ARM
登録記録あり
19
○
ARM
登録記録あり
4
○
ARM
登録記録あり
10
○
ARM
登録記録あり
153
○
ARM
登録記録あり
27
○
ARM
ARM
登録記録あり
登録記録あり
4
64
○
○
ARM
登録記録あり
12
○
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
118
37
14
○
○
○
ARM
登録記録あり
59
○
ARM
登録記録あり
54
○
ARM
登録記録あり
13
○
ARM
ARM
ARM
ARM
ARM
登録記録あり
登録記録あり
登録記録あり
登録記録あり
登録記録あり
24
13
3
67
5
○
○
○
○
○
ARM
登録記録あり
40
○
ARM
登録記録あり
27
○
ARM
登録記録あり
57
○
ARM
登録記録あり
92
○
ARM
登録記録あり
15
○
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
1
公報番号
US9448875B2
出願日
タイトル (英語)
2013/12/6 Error recovery within integrated circuit
出願人
審査･権利状況被引用回数外国出願
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
2
○
ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD 登録記録あり
ROY;CRASKE SIMON JOHN
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
登録記録あり
0
0
○
○
ARM;TUNE ANDREW
DAVID;SALISBURY SEAN
登録記録あり
JAMES;BRUCE ALISTAIR CRONE
0
○
Synchronizing exception control in a multiprocessor
ARM;JONES SIMON;TAPPLY JOE
2011/10/13 system using processing unit exception states and group
DOMINIC MICHAEL
exception states
ARM;FORD SIMON
2008/10/7 Data processing on a non-volatile mass storage device
ANDREW;STYLES CHRISTOPHER
JAMES
ARM;ANDERSSON PATRIK;EDSö
2010/6/25 Motion vector estimator
TOMAS
ARM;OTERHALS JON
ERIK;CROXFORD
2010/9/24 Graphics processing systems
DAREN;ERICSSON
LARS;NYSTAD JøRN;LILAND
EIVIND
Performance characteristic monitoring circuit and
ARM;DWIVEDI SANDEEP;HOLD
2012/7/13
method
BETINA
ARM;SEAL DAVID
2012/11/21 Conditional compare instruction
JAMES;CRASKE SIMON JOHN
ARM;NYSTAD JøRN;LJOSLAND
2009/6/3 Graphics processing systems
BORGAR;SøRGåRD EDVARD
2
US9430419B2
3
US9405939B2
4
US9407931B2
5
US9406155B2
6
US9404966B2
7
US9383999B2
8
US9367953B2
9
US9355014B2
2011/8/10
10
US9378175B2
2007/11/1 Data transfer between a master and slave
11
US9372798B2
Data processing apparatus having first and second
2014/8/21 protocol domains, and method for the data processing
apparatus
12
13
US9349209B2
US9300716B2
2011/5/27 Graphics processing systems
2012/9/20 Modelling dependencies in data traffic
14
US9294301B2
2012/9/20
Debug instruction set allocation according to processor
operating state
Selecting between contending data packets to limit
latency differences between sources
ARM;CHAUSSADE
NICOLAS;BROYER PIERRE
MICHEL;LUC PHILLIPE
ARM;FLANDERS WILLIAM
HENRY;PRASADH
RAMAMOORTHY
GURU;TUMMALA ASHOK
KUMAR;JALAL
JAMSHED;MANNAVA
PHANINDRA KUMAR
ARM;MERRY BRUCE
ARM;TUNE ANDREW DAVID
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
15
US9288258B2
2013/5/3
16
US9280675B2
17
US9256975B2
18
US9269418B2
2012/2/6
19
US9256732B2
2007/11/1
20
US9207937B2
2011/9/22
21
US9226127B2
2011/9/29
22
US9223677B2
2008/6/11
23
US9189432B2
2010/11/15
24
US9176737B2
2011/2/7
25
US9201651B2
2010/5/3
26
US9201656B2
2011/12/2
タイトル (英語)
出願人
Communication using integrated circuit interconnect
circuitry
2012/2/27 Encrypting and storing confidential data
2010/12/15 Graphics processing systems
ARM;MACE TIMOTHY
CHARLES;ROSE ANDREW
CHRISTOPHER
ARM;BRELOT JEANBAPTISTE;AIRAUD CEDRIC
DENIS ROBERT
審査･権利状況被引用回数外国出願
登録記録あり
0
○
登録記録あり
0
○
ARM;HEGGELUND
登録記録あり
FRODE;GJERMUNDNES OYSTEIN
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
○
Apparatus and method for controlling refreshing of data
in a DRAM
ARM;FELTON DONALD;ÖZER
EMRE;IDGUNJI SACHIN SATISH
ARM;HARRIS PETER
Processing efficiency on secure systems having a host WILLIAM;WILSON PETER
processor and smart card
BRIAN;THORNTON TIMOTHY
CHARLES;MARTIN DAVID PAUL
ARM;SEAL DAVID
Apparatus and method for processing a bitfield
JAMES;GRISENTHWAITE
manipulation instruction having a control value indicating
RICHARD ROY;STEPHENS NIGEL
insertion or extraction form
JOHN
GIESECKE &
Method for provisioning of a network access for a mobile DEVRIENT;ARM;SPITZ
communication device using the mobile communication
STEPHAN;STERZINGER
device
HERMANN;BROWN ROBERT
JOHN
ARM;SWAINE ANDREW
BROOKFIELD;WILLIAMS
Generation of trace data in a multi-processor system
MICHAEL JOHN;HART DAVID
KEVIN;ROSE ANDREW
CHRISTOPHER
ARM;TEYSSIER MELANIE
EMANUELLE LUCIE;BEGON
Apparatus and method for predicting target storage unit FLORENT;JAUBERT JOCELYN
FRANCOIS ORION;HUOT
NICOLAS JEAN PHILLIPPE
Controlling the execution of adjacent instructions that
ARM;REID ALASTAIR DAVID
are dependent upon a same data condition
Data processing apparatus and method having integer
ARM;CRASKE SIMON JOHN
state preservation function and floating point state
preservation function
Data processing apparatus and method for performing
ARM;BRELOT JEANregister renaming for certain data processing operations BAPTISTE;AIRAUD CéDRIC
without additional registers
DENIS ROBERT
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No.
公報番号
27
US9146901B2
28
US9170979B2
29
US9164842B2
2013/6/25 Error recovery within integrated circuit
30
US9164910B2
2008/2/21 Managing the storage of data in coherent data stores
31
US9158941B2
2006/3/16
Managing access to content in a data processing
apparatus
32
US9171594B2
2012/7/19
Handling collisions between accesses in multiport
memories
33
US9158574B2
34
US9142037B2
35
US9104479B2
36
US9105315B2
37
US9128531B2
38
US9116790B2
39
US9110643B2
40
US9087017B2
41
US9092215B2
出願日
タイトル (英語)
2011/8/26 Vector floating point argument reduction
Converging interconnect node controlling operation
related to associated future item in dependence upon
2012/3/23
data predicted based on current transaction data item
passing through
2011/11/18 Handling interrupts in data processing
2013/7/2
Methods of and apparatus for encoding and decoding
data
出願人
審査･権利状況被引用回数外国出願
ARM;NYSTAD JORN
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ARM;SALISBURY SEAN
JAMES;TUNE ANDREW DAVID
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0
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0
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ARM;CROXFORD DAREN;FELTON
DONALD;KERSHAW
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DANIEL;WILSON PETER BRIAN
0
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ARM;DHOGALE VIVEK
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0
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ARM;MANSELL DAVID
HENNAH;GLAUERT TIMOTHY
HOLROYD
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ARM;NYSTAD JORN
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ARM;NYSTAD JORN;HUGOSSON
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OLA;FLORDAL OSKAR
0
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1
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0
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ARM;THE REGENTS OF THE
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UNIVERSITY OF MICHIGAN
ARM;CHAUSSADE
NICOLAS;BROCHIER STEPHANE 登録記録あり
ERIC SEBASTIEN
ARM;LUTZ DAVID
Apparatus and method for rounding a floating-point value
2011/12/7
RAYMOND;BURGESS
to an integral floating-point value
NEIL;ROMERO SABRINA MARIE
ARM;HOLD
Controlling the voltage level on the word line to maintain BETINA;CHARAFEDDINE
2012/7/23
performance and reduce access disturbs
KENZA;LAPLANCHE YVES
THOMAS
ARM;ELLIS SEAN
2012/2/22 Operand special case handling for multi-lane processing TRISTRAM;CHARLES SIMON
ALEX;BURDASS ANDREW
2012/8/3
Methods of and apparatus for storing data in memory in
data processing systems
2012/6/11 Leakage current reduction in an integrated circuit
2011/10/13 Controlling latency and power consumption in a memory
2011/2/22
Mapping between registers used by multiple instruction
sets
ARM;IDGUNJI SACHIN
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SATISH;SANDHU BAL S
ARM;MACE TIMOTHY
CHARLES;CRAWFORD ASHLEY 登録記録あり
JOHN
ARM;GRISENTHWAITE RICHARD
登録記録あり
ROY;SEAL DAVID JAMES
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No.
公報番号
42
US9081564B2
43
US9098265B2
44
US9081581B2
45
US9075622B2
46
US9075621B2
47
US9064561B2
48
US9052909B2
49
US9021233B2
50
US9041723B2
51
US9032188B2
52
US9021172B2
53
US9032252B2
54
US9058637B2
55
US9059726B2
56
US9058179B2
出願日
タイトル (英語)
出願人
Converting scalar operation to specific type of vector
2012/4/4
ARM;REID ALASTAIR DAVID
operation using modifier instruction
Controlling an order for processing data elements during
2012/7/11
ARM;REID ALASTAIR DAVID
vector processing
ARM;HARDAGE JAMES
NOLAN;BLASCO ALLUE
2010/11/16 Size mis-match hazard detection
CONRADO;HARRIS GLEN
ANDREW
ARM;GREENHALGH PETER
2008/1/23 Reducing errors in pre-decode caches
RICHARD;ROSE ANDREW
CHRISTOPHER
ARM;SCHON
Error recovery upon reaching oldest instruction marked GUILLAUME;TEYSSIER MéLANIE
with error or upon timed expiration by flushing
EMANUELLE LUCIE;PIRY
2011/12/23
instructions in pipeline pending queue and restarting
FREDERIC CLAUDE
execution
MARIE;SCALABRINO LUCA;BULL
DAVID MICHAEL
2012/4/2 Handling of write operations within a memory device
ARM;HOLD BETINA
ARM;PIRY FREDERIC CLAUDE
MARIE;SCALABRINO
2011/12/7 Recovering from exceptions and timing errors
LUCA;SCHON
GUILLAUME;TEYSSIER MELANIE
EMANUELLE LUCIE
Interleaving data accesses issued in response to vector
2011/9/28
ARM;REID ALASTAIR DAVID
access instructions
ARM;NYSTAD JORN;LASSEN
2012/5/4 Method of and apparatus for encoding and decoding data
ANDERS
Issue policy control within a multi-threaded in-order
ARM;ÖZER EMRE;BILES STUART
2008/3/27
superscalar processor
DAVID
審査･権利状況被引用回数外国出願
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0
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0
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0
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0
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4
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0
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0
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0
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0
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0
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Data processing apparatus and method and method for
ARM;HORSNELL MATTHEW
2012/7/6 generating performance monitoring interrupt signal based JAMES;EMMONS CHRISTOPHER 登録記録あり
on first event counter and second event counter
DANIEL
0
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0
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0
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0
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0
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ARM;KALKUNTE
SHESHADRI;WILLIAMS MICHAEL 登録記録あり
JOHN
ARM;NYSTAD JORN;LASSEN
2012/5/4 Method of and apparatus for encoding and decoding data
登録記録あり
ANDERS
Apparatus and method for performing a convert-toARM;LUTZ DAVID
2012/5/11
登録記録あり
integer operation
RAYMOND;BURGESS NEIL
Retirement serialisation of status register access
2010/11/12
ARM;HARDAGE JAMES NOLAN 登録記録あり
operations
2012/8/2 Debug barrier transactions
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No.
公報番号
出願日
57
US9057761B2
2011/12/30
58
US9047184B2
2012/7/13
59
US8976177B2
2012/2/28
60
US9009208B2
2012/6/28
61
US9014496B2
2012/8/3
62
US8977837B2
2009/5/27
63
US8977815B2
2010/11/29
64
US8990282B2
2009/9/21
65
US8988443B2
2010/9/24
66
US8977820B2
2007/12/21
67
US9009450B2
2012/1/19
68
US9015719B2
2012/2/27
69
US9015424B2
2012/8/15
70
US9003123B2
2012/6/26
71
US8990518B2
2011/8/4
タイトル (英語)
出願人
ARM;WHATMOUGH PAUL
Sensing supply voltage swings within an integrated circuit NICHOLAS;BULL DAVID
MICHAEL;DAS SHIDHARTHA
ARM;BULL DAVID MICHAEL;DAS
Processing error detection within pipeline circuitry
SHIDHARTHA;WHATMOUGH
PAUL NICHOLAS
ARM;NYSTAD
Graphics processing
JORN;CHRISTENSEN ASKE
SIMON
Floating-point adder
ARM;NYSTAD JORN
ARM;NYSTAD JORN;FLORDAL
Methods of and apparatus for encoding and decoding
OSKAR;DAVIES
data in data processing systems
JEREMY;HUGOSSON OLA
ARM;MCDONALD ROBERT
Apparatus and method for early issue and recovery for a
GREGORY;MEYER PAUL
conditional load instruction having multiple outcomes
GILBERT
ARM;HEGGELUND FRODE;HOLM
Control of entry of program instructions to a fetch stage RUNE;ENGH-HALSTVEDT
within a processing pipepline
ANDREAS DUE;FEILDING
EDVARD
Apparatus and method for performing fused multiply add
ARM;LUTZ DAVID RAYMOND
floating point operation
ARM;CROXFORD
Methods of and apparatus for controlling the reading of
DAREN;ERICSSON
arrays of data from memory
LARS;OTERHALS JON ERIK
ARM;PENTON ANTONY
JOHN;WAUGH ALEX
Handling of hard errors in a cache of a data processing
JAMES;ROSE ANDREW
apparatus
CHRISTOPHER;HUGHES PAUL
STANLEY
Mixed operand size instruction processing for execution
ARM;STEPHENS NIGEL
of indirect addressing load instruction specifying
JOHN;SEAL DAVID JAMES
registers for different size operands
Scheduling of tasks to be performed by a non-coherent
ARM;ELLIOTT ROBERT
device
Write transaction management within a memory
ARM;MACE TIMOTHY CHARLES
interconnect
Data processing apparatus and method for reducing
ARM;WAUGH ALEX
storage requirements for temporary storage of data
JAMES;WINROW MATTHEW LEE
Methods of and apparatus for storing data in memory in ARM;NYSTAD JORN;HUGOSSON
data processing systems
OLA
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2
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1
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0
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0
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0
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0
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0
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0
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0
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これだけはチェック！重要出願リスト
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No.
公報番号
出願日
タイトル (英語)
出願人
Memory device and method of performing a read
2012/9/13
operation within such a memory device
ARM;CHONG YEW K;MANGAL
SANJAY
ARM;STEPHENS NIGEL
2012/1/30 Address generation in a data processing apparatus
JOHN;SEAL DAVID JAMES
Hardware resource management within a data processing ARM;WILLIAMS MICHAEL
2010/9/13
system
JOHN;BILES STUART DAVID
72
US8988954B2
73
US8954711B2
74
US8949844B2
75
US8954715B2
2012/3/16 Thread selection for multithreaded processing
76
US8965945B2
2011/2/17
77
US8966309B2
78
審査･権利状況被引用回数外国出願
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1
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0
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登録記録あり
0
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ARM;VASEKIN VLADIMIR;ROSE
ANDREW
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CHRISTOPHER;SKILLMAN ALLAN
JOHN;PENTON ANTONY JOHN
0
○
ARM;LUTZ DAVID RAYMOND
登録記録あり
0
○
2011/6/28 Distribution of an incrementing count value
登録記録あり
0
○
US8959318B2
2011/6/28
登録記録あり
0
○
79
US8957703B2
2010/4/5
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0
○
80
US8943118B2
2012/7/31
登録記録あり
0
○
81
US8959131B2
2011/9/22
登録記録あり
2
○
82
US8972701B2
2011/12/6
登録記録あり
0
○
83
US8966494B2
2012/3/16
登録記録あり
0
○
84
US8966323B2
2010/12/23
登録記録あり
0
○
85
US8966228B2
2009/3/20
登録記録あり
0
○
86
US8965946B2
2011/7/19
登録記録あり
0
○
Apparatus and method for performing floating point
addition
ARM;SWAINE ANDREW
BROOKFIELD
ARM;GRISENTHWAITE RICHARD
Illegal mode change handling
ROY
ARM;RIEN MIKAEL;DUBY JEANProtecting lower voltage domain devices during operation CLAUDE;LEYMARIE
in a higher voltage domain
FLORA;BLANC
FABRICE;PADILLA THIERRY
Data processing apparatus and method for reducing the ARM;BURGESS NEIL;LUTZ DAVID
size of a lookup table
RAYMOND
ARM;NYSTAD JORN;ENGHNumber format pre-conversion instructions
HALSTVEDT ANDREAS
DUE;CHARLES SIMON ALEX
Setting zero bits in architectural register for storing
ARM;HARDAGE JAMES
destination operand of smaller size based on
NOLAN;HARRIS GLEN
corresponding zero flag attached to renamed physical
ANDREW;GLASS MARK
register
CARPENTER
ARM;MAKLJENOVIC
Apparatus and method for processing threads requiring
NEBOJSA;JAMES BENJAMIN
resources
CHARLES
Monitoring multiple data transfers
ARM;HORLEY JOHN MICHAEL
ARM;CRASKE SIMON
Instruction fetching following changes in program flow
JOHN;PATHIRANE CHILODA
ASHAN SENERATH
Data processing apparatus and method for performing a ARM;LUTZ DAVID
reciprocal operation on an input value to produce a result RAYMOND;HINDS CHRISTOPHER
value
NEAL
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No.
公報番号
出願日
タイトル (英語)
出願人
Coherency controller and method for data hazard
handling for copending data access requests
87
US8949547B2
2011/8/8
88
US8935485B2
2011/8/8 Snoop filter and non-inclusive shared cache memory
89
US8914616B2
Exchanging physical to logical register mapping for
2011/12/2 obfuscation purpose when instruction of no operational
impact is executed
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
JAMSHED;PRASADH
RAMAMOORTHY GURU;FILIPPO
MICHAEL ALAN
ARM;JALAL JAMSHED;FEERO
BRETT STANLEY;WERKHEISER
MARK DAVID;FILIPPO MICHAEL
ALAN
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0
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1
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0
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0
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0
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1
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1
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0
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2
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ARM;PELLOIE JEAN
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LUC;LAPLANCHE YVES THOMAS
0
○
ARM;PERSSON ERIK;HUGOSSON
登録記録あり
OLA;BJöRKLUND ANDREAS
0
○
登録記録あり
0
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登録記録あり
0
○
ARM;CRASKE SIMON JOHN
ARM;JONES SIMON;ENGHSwitching between dedicated function hardware and use HALSTVEDT
2011/6/9
of a software routine to generate result data
ANDREAS;CHRISTENSEN ASKE
SIMON
ARM;MYERS JAMES
Power controlling integrated circuit and retention
2010/11/22
EDWARD;FLYNN DAVID
switching circuit
WALTER;BIGGS JOHN PHILIP
ARM;NYSTAD JORN;HOLM
Method and apparatus for rendering a stroked curve for
2009/10/6
RUNE;CHRISTENSEN ASKE
display in a graphics processing system
SIMON
ARM;NYSTAD JORN;HOLM
2009/10/6 Rendering stroked curves in graphics processing systems RUNE;CHRISTENSEN ASKE
SIMON
ARM;BURGESS NEIL;LUTZ DAVID
2012/6/14 Data processing apparatus and method
RAYMOND
Transaction routing device and method for routing
2012/2/27
ARM;LAUGHTON ARTHUR
transactions in an integrated circuit
90
US8922568B2
91
US8922247B2
92
US8928668B2
93
US8928667B2
94
US8892623B2
95
US8930601B2
96
US8924766B2
2012/2/28
97
US8924686B2
2009/10/8 Memory management unit
98
US8924612B2
99
US8914615B2
Analysing timing paths for circuits formed of standard
cells
Apparatus and method for providing a bidirectional
2012/4/4 communications link between a master device and a
slave device
Mapping same logical register specifier for different
2011/12/2 instruction sets with divergent association to
architectural register file using common address format
審査･権利状況被引用回数外国出願
ARM;MAJI PARTHA
PRASUN;MELLOR STEVEN
RICHARD
ARM;HARRIS GLEN
ANDREW;HARDAGE JAMES
NOLAN;GLASS MARK
CARPENTER
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No.
公報番号
100
US8892923B2
101
US8892801B2
出願日
タイトル (英語)
出願人
Data processing apparatus and method for maintaining a
ARM;HUGHES PAUL
2011/12/20 time count value in normal and power saving modes of
STANLEY;PARKER JASON
operation
Arbitration circuity and method for arbitrating between a
2012/5/23
ARM;TUNE ANDREW DAVID
plurality of requests for access to a shared resource
US8856408B2
103
US8874975B2
104
US8874883B2
105
US8873209B2
106
US8887001B2
107
US8868962B2
108
US8831341B2
2011/10/5 Image encoding using base colors on luminance line
109
US8839038B2
2012/2/14 Diagnosing code using single step execution
110
US8819378B2
111
US8803898B2
112
US8812997B2
2010/10/5
Reduced latency barrier transaction requests in
interconnects
102
2011/10/13 Tracing of a data processing apparatus
2011/7/28 Debugging of a data processing apparatus
2011/12/19
Integrated circuit and method of providing electrostatic
discharge protection within such an integrated circuit
2011/2/14 Trace data priority selection
2012/2/8 Monitoring circuit and method
Data processing apparatus and method for performing
2011/11/14 memory transactions within such a data processing
apparatus
2009/12/17 Forming a windowing display in a frame buffer
2011/5/18 Structural feature formation within an integrated circuit
審査･権利状況被引用回数外国出願
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0
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0
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ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
2
○
ARM;GILKERSON PAUL
ANTHONY;HORLEY JOHN
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MICHAEL;GIBBS MICHAEL JOHN
0
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0
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1
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0
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0
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0
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登録記録あり
2
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登録記録あり
0
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4
○
0
○
ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD
ROY
ARM;BLANC FABRICE;PAULY
MATTHIEU;POTTIER FLORA
ARM;HORLEY JOHN
MICHAEL;WILLIAMS MICHAEL
JOHN;KNEEBONE KATHERINE
ELIZABETH;REID ALASTAIR
DAVID
ARM;MYERS JAMES
EDWARD;FLYNN DAVID
WALTER;SANDHU BAL S
ARM;BERENT ANTHONY NEIL
ARM;WILLIAMS MICHAEL
JOHN;GRISENTHWAITE RICHARD
ROY
ARM;CRASKE SIMON JOHN
ARM;SHREINER DAVID
ROBERT;DEVEREUX IAN
VICTOR;SøRG{DOT OVER (A)}RD 登録記録あり
EDVARD;OLSON THOMAS
JEREMY
ARM;YERIC GREGORY MUNSON 登録記録あり
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No.
公報番号
113
US8824215B2
114
US8839057B2
115
US8838929B2
116
US8830783B2
117
US8826097B2
118
US8826079B2
119
US8817433B2
120
US8775754B2
121
US8788775B2
122
US8766991B2
123
US8788887B2
124
US8775824B2
125
US8762744B2
126
US8769251B2
出願日
タイトル (英語)
2012/2/1 Data storage circuit that retains state during precharge
出願人
審査･権利状況被引用回数外国出願
ARM;FREDERICK JR. MARLIN
WAYNE;ALAM AKHTAR
WASEEM;PAL SUMANA
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0
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1
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4
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2
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0
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1
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0
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ARM;LUC PHILIPPE;LATAILLE
NORBERT BERNARD EUGé
登録記録あり
NE;BEGON
FLORENT;CHAUSSADE NICOLAS
0
○
Integrated circuit and method for testing memory on the
ARM;HUGHES PAUL STANLEY
integrated circuit
Allocation and deallocation of bounded time relative
2011/10/5
ARM;FELL ROBIN
portions of a graphics memory
ARM;IDGUNJI SACHIN
SATISH;GAJJEWAR HEMANGI
2011/1/3 Improving read stability of a semiconductor memory
UMAKANT;SCHUPPE VINCENT
PHILLIPE;CHONG YEW
KEONG;CHEN HSIN-YU
ARM;ÖZER EMRE;IDGUNJI
2011/3/30 Memory scrubbing
SACHIN SATISH
Data processing apparatus and method for identifying
ARM;GILDAY DAVID
2011/12/16
debug events
MICHAEL;CRASKE SIMON JOHN
Electrostatic discharge protection device having an
ARM;PADILLA THIERRY;BLANC
2011/7/28 intermediate voltage supply for limiting voltage stress on
FABRICE;DUBY JEAN-CLAUDE
components
ARM;CAMPBELL MICHAEL
Memory controller and method of selecting a transaction ANDREW;WRIGLEY
2011/6/24
using a plurality of ordered lists
CHRISTOPHER EDWIN;FEERO
BRETT STANLEY
Memory access control using redundant and nonARM;GRISENTHWAITE RICHARD
2011/6/28
redundant encoding
ROY
Processing order with integer inputs and floating point
ARM;ENGH-HALSTVEDT
2011/5/25
inputs
ANDREAS DUE;NYSTAD JøRN
ARM;GILKERSON PAUL
Data processing apparatus, trace unit and diagnostic
2011/8/3
ANTHONY;HORLEY JOHN
apparatus
MICHAEL
Protecting the security of secure data sent from a
ARM;KERSHAW DANIEL;PAVER
2008/1/2 central processor for processing by a further processing
NIGEL CHARLES
device
ARM;FORD SIMON
Energy management system configured to generate
ANDREW;BRADLEY DARYL
2008/6/3 energy management information indicative of an energy
WAYNE;MILNE GEORGE
state of processing elements
JAMES;HORLEY JOHN MICHAEL
2011/2/3
Data processing apparatus and method for converting
2006/12/13
data values between endian formats
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
127
US8769307B2
2005/6/1 Secure operation indicator
128
US8782378B2
2010/9/14 Dynamic instruction splitting
Apparatus and method for determining variation in a
2011/11/16
predetermined physical property of a circuit
129
US8779787B2
130
US8773593B2
2011/1/3 Noise reduction filter circuitry and method
131
US8769344B2
2011/6/13 Tracing speculatively executed instructions
132
US8732400B2
2010/10/5 Data store maintenance requests in interconnects
133
US8732499B2
2011/5/27
134
US8719555B2
135
US8719553B2
136
US8717366B2
State retention circuit adapted to allow its state integrity
to be verified
Method for overcoming livelock in a multi-threaded
2008/1/31
system
Method for re-circulating a fragment through a rendering
2008/1/31
pipeline
2010/7/27 Method and apparatus for rendering a stroked curve
137
US8725953B2
2009/1/21
138
US8743135B2
2009/10/6
139
US8756377B2
2010/2/2
140
US8751833B2
2010/4/30
141
US8742827B2
2011/5/24
142
US8738971B2
2011/12/7
143
US8732523B2
2011/10/24
ARM;FELTON DONALD;MCNIVEN
JAMES I
ARM;CHAUSSADE
NICOLAS;TEYSSIER RéMI
ARM;LAPLANCHE YVES
THOMAS
ARM;PERSSON ERIK;EDGREN
PER
ARM;GILKERSON PAUL
ANTHONY;HORLEY JOHN
MICHAEL
審査･権利状況被引用回数外国出願
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0
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登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
2
○
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
2
○
ARM;FLYNN DAVID WALTER
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
0
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0
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4
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0
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0
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2
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登録記録あり
0
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登録記録あり
2
○
登録記録あり
0
○
ARM NORWAY AS;NYSTAD
JORN;HEGGELUND FRODE
ARM NORWAY AS;NYSTAD
JORN;HEGGELUND FRODE
ARM;MERRY BRUCE
ARM;PAVER NIGEL C;BILES
Local cache power control within a multiprocessor
STUART D;WELTON KEVIN
system
P;MEYER PAUL G
Graphics processing systems
ARM;NYSTAD JøRN;HOLM RUNE
ARM;CRASKE SIMON
JOHN;PENTON ANTONY
Area and power efficient data coherency maintenance
JOHN;PIERRON LOIC;ROSE
ANDREW CHRISTOPHER
Data processing system
ARM;HILL STEPHEN JOHN
ARM;VAN WINKELHOFF
Power gating circuit
NICOLAAS KLARINUS
JOHANNES;BRUN MIKAEL
ARM;PIRY FREDERIC CLAUDE
Limiting certain processing activities as error rate
MARIE;SCALABRINO LUCA;BULL
probability rises
DAVID MICHAEL
Data processing apparatus and method for analysing
ARM;ÖZER EMRE;SAZEIDES
transient faults occurring within storage elements of the YIANNAKIS;KERSHAW
data processing apparatus
DANIEL;BILES STUART DAVID
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
144
US8717078B2
2012/6/13
145
US8707056B2
2011/9/21
146
US8713371B2
2011/11/15
147
US8677107B2
2011/3/7
148
US8698828B2
2009/6/3
149
US8707106B2
2011/6/9
150
US8713375B2
2011/5/13
151
US8706936B2
2011/11/14
152
US8706965B2
タイトル (英語)
出願人
ARM;IDGUNJI SACHIN
Sequential latching device with elements to increase hold
SATISH;AITKEN ROBERT
times on the diagnostic data path
CAMPBELL;IQBAL IMRAN
Security provision for a subject image displayed in a nonARM;FELTON DONALD
secure domain
ARM;WILLIAMS MICHAEL
Controlling generation of debug exceptions
JOHN;GRISENTHWAITE RICHARD
ROY
ARM;GRISENTHWAITE RICHARD
Apparatus and method for handling exception events
ROY
ARM;PLOWMAN
Graphics processing systems
EDWARD;NYSTAD Jø
RN;LJOSLAND BORGAR
ARM;HORLEY JOHN M;SWAINE
Key allocation when tracing data processing systems
ANDREW B;GILKERSON PAUL A
ARM;GILKERSON PAUL
Correlating trace data streams
ANTHONY;HORLEY JOHN
MICHAEL
Integrated circuit having a bus network, and method for ARM;PRASADH RAMAMOORTHY
the integrated circuit
GURU
審査･権利状況被引用回数外国出願
登録記録あり
4
○
登録記録あり
34
○
登録記録あり
0
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登録記録あり
2
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0
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
3
○
Apparatus and method for handling access operations
ARM;PIRY FREDERIC
2011/6/3 issued to local cache structures within a data processing CLAUDE;MOUTON LOUIS-MARIE 登録記録あり
apparatus
VINCENT;SCALABRINO LUCA
0
○
0
○
4
○
1
○
登録記録あり
0
○
ARM;SAZEIDES YIANNAKIS;ÖZER
EMRE;KERSHAW DANIEL;BRELOT 登録記録あり
JEAN-BAPTISTE
3
○
ARM;REED BRIAN WILLIAM
1
○
System for efficiently tracing data in a data processing
2010/12/27
system
153
US8677104B2
154
US8681168B2
155
US8698820B2
2009/6/5 Graphics processing systems
156
US8713292B2
Reducing energy and increasing speed by an instruction
2011/2/7 substituting subsequent instructions with specific
function instruction
157
US8694862B2
2012/4/20
158
US8680912B2
2012/7/17 Level shifting circuitry
2010/1/12 Methods of and apparatus for processing graphics
Data processing apparatus using implicit data storage
data storage and method of implicit data storage
ARM;GIBBS
MICHAEL;GILKERSON PAUL
登録記録あり
ANTHONY;HORLEY JOHN
MICHAEL
ARM;NYSTAD JøRN;LANGTIND
FRANK;TAPPLY JOE;CROXFORD 登録記録あり
DAREN
ARM;COX ANDREW
登録記録あり
HELGE;ELLIOT ROBERT;FELL
ROBIN;ELLIS SEAN
ARM;NYSTAD JORN
Copyright 2016 Innovation Research Corporation
登録記録あり
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
Self-initializing on-chip data processing apparatus and
2012/8/10 method of self-initializing an on-chip data processing
apparatus
Communication within an integrated circuit including an
2011/7/7
array of interconnected programmable logic elements
159
US8680900B2
160
US8675681B2
161
US8675006B2
2009/8/11
162
US8639960B2
2011/5/27 Verifying state integrity in state retention circuits
163
US8665009B2
2012/7/31
Integrated circuit and method for controlling load on the
output from on-chip voltage generation circuitry
164
US8661225B2
2010/1/19
Data processing apparatus and method for handling
vector instructions
165
US8638157B2
2011/5/23 Level shifting circuitry
166
US8650470B2
167
US8656078B2
Apparatus and method for communicating between a
central processing unit and a graphics processing unit
2010/10/25 Error recovery within integrated circuit
Transaction identifier expansion circuitry and method of
operation of such circuitry
Data processing apparatus and method for performing
2008/3/18
multi-cycle arbitration
2011/5/9
168
US8667199B2
169
US8661232B2
2010/9/16 Register state saving and restoring
170
US8660173B2
2010/10/7 Video reference frame retrieval
出願人
審査･権利状況被引用回数外国出願
ARM;WANG BINGDA
BRANDON;GITCHEV KOSTADIN
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
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登録記録あり
0
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登録記録あり
1
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
4
○
0
○
0
○
0
○
ARM;HILL STEPHEN
JOHN;MULLER MICHAEL PETER
ARM;FORD SIMON
ANDREW;ELLIS SEAN
TRISTRAM;PLOWMAN EDWARD
CHARLES
ARM;FLYNN DAVID
WALTER;IDGUNJI SACHIN
SATISH
ARM;MYERS JAMES
EDWARD;SAVANTH
PARAMESHWARAPPA ANAND
KUMAR;FLYNN DAVID
WALTER;HOWARD DAVID
WILLIAM;SANDHU BAL S
ARM;BJöRKLUND
ANDREAS;PERSSON
ERIK;HUGOSSON OLA
ARM;DUBY JEAN-CLAUDE;RIEN
MIKAEL;GUYONNET DAMIEN
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;FLAUTNER
KRISZTIAN;AUSTIN TODD
MICHAEL;BLAAUW DAVID
THEODORE;MUDGE TREVOR
NIGEL;BULL DAVID
ARM;LIM SEOW CHUAN
ARM;GWILT DAVID
登録記録あり
JOHN;INGRAM GRAEME LESLIE
ARM;PENTON ANTONY
登録記録あり
JOHN;AXFORD SIMON
ARM;BJöRKLUND
ANDREAS;PERSSON ERIK;BORG
登録記録あり
PONTUS;WALLANDER MATS
PETTER
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
171
US8640008B2
2011/12/23 Error recovery in a data processing apparatus
172
US8639987B2
173
US8639975B2
174
US8638622B2
175
US8635411B2
176
US8635406B2
177
US8634440B2
2010/8/23 Time-division multiplexing processing circuitry
178
US8630358B2
2012/3/20
2011/2/18
Data processing apparatus and method using monitoring
circuitry to control operating parameters
2010/11/17 Error management within a data processing system
Apparatus and method for receiving a differential data
strobe signal
Data processing apparatus and method for managing
2011/7/18
coherency of cached data
Data processing apparatus and method for providing
2012/3/8
target address information for branch instructions
2011/7/6
Data packet flow control across an asynchronous clock
domain boundary
179
US8607006B2
2010/10/5 Barrier transactions in interconnects
180
US8621242B2
181
US8621272B2
2010/7/7 Integrated circuit with error repair and fault tolerance
182
US8621336B2
2008/8/1 Error correction in a set associative storage device
183
US8619554B2
2006/8/4 Interconnecting initiator devices and recipient devices
2010/10/14 Display of a verification image to confirm security
ARM;SCHON
GUILLAUME;SCALABRINO
LUCA;PIRY FREDERIC CLAUDE
MARIE;BULL DAVID MICHAEL
ARM;WHATMOUGH PAUL
NICHOLAS;BULL DAVID
MICHAEL;DAS SHIDHARTHA
ARM;WHATMOUGH PAUL
NICHOLAS;BULL DAVID
MICHAEL;DAS
SHIDHARTHA;KERSHAW DANIEL
ARM;WANG BINGDA B;GITCHEV
KOSTADIN
ARM;FLANDERS WILLIAM
HENRY;KHOSA VIKRAM
ARM;GREENHALGH PETER
R;CRASKE SIMON J
ARM;SAUNDERS SPENCER
J;DILLON LIAM;JANTA RAFAL J
ARM;MAJI PARTHA
PRASUN;MELLOR STEVEN
RICHARD
審査･権利状況被引用回数外国出願
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0
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登録記録あり
4
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登録記録あり
2
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登録記録あり
3
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登録記録あり
0
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登録記録あり
0
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登録記録あり
0
○
登録記録あり
0
○
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
0
○
登録記録あり
5
○
登録記録あり
8
○
登録記録あり
0
○
登録記録あり
0
○
ARM;BROWN ROBERT;FELTON
DONALD;MCNIVEN JAMES IAN
ARM;DAS SHIDHARTHA;BULL
DAVID MICHAEL;OZER EMRE
ARM;CRASKE SIMON
JOHN;ROSE ANDREW
CHRISTOPHER;HUGHES PAUL
STANLEY;PENTON ANTONY
JOHN;YORK RICHARD;FORD
SIMON ANDREW;BILES STUART
DAVID;WAUGH ALEX JAMES
ARM;TUNE ANDREW
DAVID;HOTCHKISS ROBIN
Copyright 2016 Innovation Research Corporation
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共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
184
US8615687B2
Data processing system and method for regulating a
2011/1/10 voltage supply to functional circuitry of the data
processing system
185
US8611172B2
2012/5/21
Controlling a voltage level of an access signal to reduce
access disturbs in semiconductor memories
186
US8601167B2
2010/10/13
Maintaining required ordering of transaction requests in
interconnects using barriers and hazard checks
2
○
登録記録あり
0
○
ARM;RIOCREUX PETER ANDREW 登録記録あり
2
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
5
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
0
○
ARM;PIRY FREDERIC CLAUDE
MARIE;MOUTON LOUIS-MARIE
Apparatus and method for mapping architectural registers
2010/6/15
VINCENT;SCALABRINO
登録記録あり
to physical registers
LUCA;GRISENTHWAITE RICHARD
ROY;MANSELL DAVID HENNAH
1
○
Checkpointing long latency instruction as fake branch in
branch prediction mechanism
US8578139B2
2010/8/5
188
US8594177B2
2010/8/31
189
US8566563B2
2011/3/14 Translation table control
190
US8589934B2
191
US8589631B2
2011/9/12 Coherency control with writeback ordering
192
US8589927B2
2011/2/14
193
US8583897B2
2009/2/2
US8578136B2
審査･権利状況被引用回数外国出願
登録記録あり
187
194
ARM;SANDHU BAL S;IDGUNJI
SACHIN SATISH;FLYNN DAVID
WALTER
ARM;SHYANMUGAM
AMARANTH;MAITI
BIKAS;SCHUPPE VINCENT
PHILLIPE;CHONG YEW
KEONG;KINKADE MARTIN
JAY;CHEN HSIN-YU
2011/4/1
Reducing reference frame data store bandwidth
requirements in video decoders
Controlling priority levels of pending threads awaiting
processing
Method, apparatus and trace module for generating
timestamps
ARM;CHAUSSADE
NICOLAS;BEGON
FLORENT;TEYSSIER MéLANIE
EMANUELLE LUCIE;TEYSSIER Ré
MI;JAUBERT JOCELYN
FRANCOIS ORION
ARM;BJöRKLUND
ANDREAS;HUGOSSON OLA
ARM;GRISENTHWAITE RICHARD
ROY
ARM;MAKLJENOVIC
NEBOJSA;FIELDING
EDVARD;ENGH-HALSTVEDT
ANDREAS
ARM;LAYCOCK CHRISTOPHER
WILLIAM;HARRIS ANTONY
JOHN;MATHEWSON BRUCE
JAMES;BILES STUART DAVID
ARM;WILLIAMS MICHAEL
JOHN;HORLEY JOHN
MICHAEL;ASHFIELD EDMOND
JOHN SIMON
Register file with circuitry for setting register entries to a
ARM;CRASKE SIMON JOHN
predetermined value
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
2010/10/29
タイトル (英語)
出願人
Apparatus and method for performing multiplyaccumulate operations
195
US8595280B2
196
US8572329B2
2005/10/4 Multi-region default memory map
197
US8601485B2
2011/5/25
198
US8601324B2
199
US8599626B2
Data processing apparatus and method for processing a
received workload in order to generate result data
2010/8/2 Storage and output of trace data
2011/12/7
Memory device and a method of operating such a
memory device in a speculative read mode
Terminating barriers in streams of access requests to a
data store while maintaining data consistency
200
US8589638B2
2011/7/19
201
US8582389B2
2011/6/15 Write assist in a dual write line semiconductor memory
202
US8582340B2
2012/1/12
Word line and power conductor within a metal layer of a
memory cell
203
US8561169B2
2007/12/5
Data processing apparatus and method for managing
access to a display buffer
204
US8533685B2
2011/10/26
205
US8549199B2
2010/9/15
206
US8548962B2
2011/8/15
207
US8533505B2
2010/3/1
208
US8532192B2
2010/7/14
209
US8549325B2
2008/5/2
Processing apparatus, trace unit and diagnostic
apparatus
Data processing apparatus and a method for setting
priority levels for transactions
Data compression and decompression using relative and
absolute delta values
Data processing apparatus and method for transferring
workload between source and destination processing
circuitry
Video processing apparatus and a method of processing
video data
Reducing information leakage between processes sharing
a cache
ARM;SYMES DOMINIC
HUGO;WILDER MLADEN;LARRI
GUY
ARM;AXFORD SIMON;CRASKE
SIMON JOHN;KIMELMAN PAUL
ARM;ENGH-HALSTVEDT
ANDREAS DUE;NYSTAD JøRN
ARM;HORLEY JOHN
MICHAEL;HINDS CHRISTOPHER
NEAL
審査･権利状況被引用回数外国出願
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0
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登録記録あり
0
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登録記録あり
3
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
2
○
登録記録あり
5
○
ARM;MACE TIMOTHY CHARLES
登録記録あり
5
○
ARM;TAPPLY JOE D.;LILAND
EIVIND;ELLIS SEAN T.
登録記録あり
0
○
ARM;GREENHALGH PETER
RICHARD
登録記録あり
2
○
登録記録あり
0
○
登録記録あり
1
○
ARM;HOLD BETINA
ARM;CAMPBELL MICHAEL
ANDREW;RIOCREUX PETER
ANDREW
ARM;GAJJEWAR HEMANGI
UMAKANT;IDGUNJI SACHIN
SATISH;YEUNG GUS
ARM;CHONG YEW
KEONG;YEUNG GUS
ARM;HARRIS PETER
WILLIAM;WILSON PETER
BRIAN;MARTIN DAVID
PAUL;THORNTON TIMOTHY
CHARLES
ARM;HORLEY JOHN
MICHAEL;CRASKE SIMON
JOHN;GIBBS MICHAEL
JOHN;GILKERSON PAUL
ANTHONY
ARM;PERSSON ERIK;EDSö
TOMAS
ARM;HARRIS PETER
WILLIAM;MARTIN DAVID PAUL
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これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;IDGUNJI SACHIN
Apparatus and method for detecting an approaching error SATISH;DAS SHIDHARTHA;BULL
2010/6/7
登録記録あり
condition
DAVID MICHAEL;AITKEN
ROBERT CAMPBELL
210
US8555124B2
211
US8549633B2
212
US8549257B2
213
US8542939B2
214
US8519775B2
215
US8502568B2
216
US8493810B2
217
US8493120B2
218
US8484497B2
2010/7/27 Power supply control within an integrated circuit
219
US8497702B2
2011/4/15
220
US8477148B2
221
US8468394B2
222
US8468393B2
2
○
登録記録あり
0
○
登録記録あり
0
○
登録記録あり
3
○
登録記録あり
10
○
登録記録あり
1
○
登録記録あり
0
○
登録記録あり
5
○
ARM;PATIL SANJAY
BHAGWAN;GOMEZ
登録記録あり
VALENTINA;SEBASTINE ANTONY
6
○
登録記録あり
2
○
登録記録あり
4
○
登録記録あり
0
○
登録記録あり
2
○
ARM;CHUAN LIM SEOW;MACE
TIMOTHY CHARLES
Area efficient arrangement of interface devices within an ARM;MISHRA VIKAS;WANG
2011/1/10
integrated circuit
BINGDA BRANDON
2011/8/3 Security controller
Methods of and apparatus for using tree representations
ARM;NYSTAD JORN;FLORDAL
2011/8/4 for representing arrays of data elements for encoding and
OSKAR;DAVIES JEREMY
decoding data in data processing systems
ARM;IDGUNJI SACHIN
SATISH;SANDHU BAL S
ARM;DWIVEDI SANDEEP;KUMAR
2010/8/17 Receiver circuit with high input voltage protection
NIDHIR;CHERUKU SRIDHAR
ARM;VAN WINKELHOFF
NICOLAAS KLARINUS
2011/5/9 Memory circuitry with write boost and write assist
JOHANNES;GOUYA GERALD
JEAN LOUIS;CHEN HSIN-YU
Storage circuitry and method with increased resilience to ARM;CHOUDHURY MIHIR
2011/3/10
single event upsets
RAJANIKANT;CHANDRA VIKAS
2011/7/28 Voltage regulation of a virtual power rail
Power control of an integrated circuit including an array
of interconnected configurable logic elements
2009/10/6 Graphics processing systems
ARM;HILL STEPHEN
JOHN;MULLER MICHAEL PETER
ARM;NYSTAD JøRN;HOLM RUNE
ARM;BRADLEY DARYL
Method of tracing selected activities within a data
WAYNE;HORLEY JOHN
2008/11/3 processing system by tagging selected items and tracing
MICHAEL;WOODHOUSE
the tagged items
SHELDON JAMES
ARM;HORLEY JOHN
Triggering diagnostic operations within a data processing
2007/6/28
MICHAEL;SWAINE ANDREW
apparatus
BROOKFIELD
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No.
公報番号
出願日
タイトル (英語)
出願人
Translation of SIMD instructions in a data processing
system
223
US8505002B2
2007/9/27
224
US8498373B2
2012/1/12 Generating a regularly synchronised count value
225
US8478947B2
226
US8479033B2
2010/6/16 Power supply detection circuitry and method
227
US8510356B2
2010/3/16 Identifier selection
228
US8509015B2
229
US8504961B2
230
US8502561B2
231
US8499106B2
232
US8499017B2
233
US8490107B2
2005/7/5 Memory controller
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;YEHIA
SAMI;FLAUTNER
KRISZTIAN;CLARK
NATHAN;HORMATI
AMIR;MAHLKE SCOTT
ARM;HORLEY JOHN
MICHAEL;WOODHOUSE
SHELDON JAMES;WILLIAMS
MICHAEL JOHN;KALKUNTE
SHESHADRI;ROSE ANDREW
CHRISTOPHER
ARM;INGRAM GRAEME
LESLIE;QUINN IAN JAMES
ARM;GAJJEWAR HEMANGI
UMAKANT;YEUNG GUS
ARM;HORLEY JOHN
MICHAEL;SWAINE ANDREW
BROOKFIELD;WILLIAMS
MICHAEL JOHN
Using a precharge characteristics of a node to validate a
2011/12/16 previous data/signal value represented by a discharge of ARM;HOLD BETINA K. M.
said node
2011/5/18 Integrated circuit with timing adjustment mechanism
ARM;JAVERLIAC VIRGILE
ARM;HOWARD DAVID
2011/7/1 Signal value storage circuitry with transition detector
WILLIAM;BULL DAVID
MICHAEL;DAS SHIDHARTHA
ARM;POUBLAN SERGE
2010/6/24 Buffering of a data stream
HENRI;SWAINE ANDREW
BROOKFIELD
ARM;PENTON ANTONY
Apparatus and method for performing fused multiply add
2009/8/12
JOHN;CRASKE SIMON
floating point operation
JOHN;CAULFIELD IAN MICHAEL
ARM;JALAL
JAMSHED;WERKHEISER MARK
DAVID;FEERO BRETT
Processing resource allocation within an integrated
STANLEY;FILIPPO MICHAEL
2011/8/8 circuit supporting transaction requests of different
ALAN;PRASADH
priority levels
RAMAMOORTHY
GURU;MANNAVA PHANINDRA
KUMAR
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No.
公報番号
234
US8488369B2
235
US8484508B2
236
US8473819B2
237
US8473717B2
238
US8471612B1
239
US8468405B2
240
US8448251B2
241
US8443170B2
242
US8463958B2
243
US8441301B2
244
US8421501B1
出願日
2011/3/10
タイトル (英語)
出願人
Method of altering distribution of a chosen characteristic ARM;CHANDRA VIKAS;AITKEN
of a plurality of memory cells forming a memory device
ROBERT CAMPBELL
ARM;PENTON ANTONY
Data processing apparatus and method for providing fault
JOHN;FORD SIMON
2010/1/14 tolerance when executing a sequence of data processing
ANDREW;ROSE ANDREW
operations
CHRISTOPHER
ARM;KERSHAW DANIEL;BULL
2011/3/24 Error management
DAVID MICHAEL;WILDER
MLADEN
Coprocessor reset controller with queue for storing
ARM;HUGOSSON OLA;PERSSON
2010/2/3 configuration information of subsequent sessions prior to
ERIK;BORG PONTUS
completion of current session
Signal value storage circuitry with transition error
ARM;BULL DAVID MICHAEL;DAS
2012/7/10
detector
SHIDHARTHA
ARM;MCLAURIN TERESA
2010/12/22 Integrated circuit testing
LOUISE;WILLIAMS GERARD
RICHARD
Method and apparatus for processing and displaying
ARM;HARRIS PETER
2009/3/25
secure and non-secure data
WILLIAM;MARTIN DAVID PAUL
ARM;WILDER MLADEN;SYMES
Apparatus and method for performing SIMD multiply2009/9/17
DOMINIC HUGO;BRUCE
accumulate operations
RICHARD EDWARD
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
JAMSHED;PRASADH
Dynamic resource allocation for transaction requests
2011/8/8
RAMAMOORTHY GURU;FILIPPO
issued by initiator devices to recipient devices
MICHAEL ALAN;MATHEWSON
BRUCE JAMES;MACE TIMOTHY
CHARLES
ARM;DUBY JEAN2011/12/7 Cascoded level shifter protection
CLAUDE;BLANC FABRICE
Digital data handling in a circuit powered in a high voltage ARM;RIEN MIKAEL;DUBY JEAN2011/12/7 domain and formed from devices designed for operation CLAUDE;GUYONNET
in a lower voltage domain
DAMIEN;PADILLA THIERRY
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2
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2
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0
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245
US8463966B2
2010/10/13
Synchronising activities of various components in a
distributed system
ARM;RIOCREUX PETER
ANDREW;MATHEWSON BRUCE
JAMES;LAYCOCK CHRISTOPHER 登録記録あり
WILLIAM;GRISENTHWAITE
RICHARD ROY
246
US8433961B2
2010/5/6
Data processing apparatus and method for testing a
circuit block using scan chains
ARM;HUGHES PAUL STANLEY
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No.
公報番号
出願日
247
US8429457B2
248
US8427245B2
249
US8427214B2
250
US8423752B2
251
US8422262B2
252
US8421821B2
253
US8421516B2
2010/2/18
254
255
US8421513B2
US8450954B2
2011/6/1 Master-slave flip-flop circuit
2011/9/19 Electronically controlled universal motor
256
US8456199B2
257
US8456223B2
258
US8427198B1
259
US8456140B2
2010/7/14
Power control apparatus and method for controlling a
supply voltage for an associated circuit
260
US8452907B2
2009/9/25
Data processing apparatus and method for arbitrating
access to a shared resource
261
US8463834B2
2009/11/3
Floating point multiplier with first and second partial
product shifting circuitry for result alignment
2009/12/11
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;HARRIS ANTONY
Use of statistical representations of traffic flow in a data
JOHN;CROSSLEY SIMON;BRUCE 登録記録あり
processing system
ALISTAIR CRONE
6
○
登録記録あり
3
○
2010/12/28 Clock state independent retention master-slave flip-flop ARM;PAL SUMANA
登録記録あり
2
○
Apparatus and method for performing permutation
operations in which the ordering of one of a first group
2008/12/16 and a second group of data elements is preserved and
the ordering of the other group of data elements is
changed
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1
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4
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1
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0
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1
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4
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1
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2011/6/2 Ultra low power oscillator
ARM;SANDHU BAL S
2011/4/7 Generating ROM bit cell arrays
2011/12/22 Differential encoding using a 3D graphics processor
Apparatus and method providing an interface between a
first voltage domain and a second voltage domain
2010/12/20 Reducing current leakage in a semiconductor device
2011/6/24 Integrated circuit with power gating
2011/12/16 Reduced quantization error I/O resistor calibrator
ARM;SYMES DOMINIC
HUGO;WILDER MLADEN
ARM;NEVERS YANNICK
MARC;SCHUPPE VINCENT
PHILIPPE
ARM NORWAY AS;NYSTAD
JORN;SORGARD
EDVARD;LJOSLAND
BORGAR;BLAZEVIC MARIO
ARM;KUMAR NIDHIR;CHERUKU
SRIDHAR;PRABHU
MANJUNATHA GOVINDA
ARM;PAL SUMANA
ARM;PIETROMONACO DAVID V
ARM;YEUNG GUS;GAJJEWAR
HEMANGI UMAKANT
ARM;MYERS JAMES
EDWARD;FLYNN DAVID WALTER
ARM;CHERUKU
SRIDHAR;SUBRAMANIAN
SIVARAMAKRISHNAN;KUMAR
NIDHIR
ARM;PATIL SANJAY
BHAGWAN;FREDERICK JR.
MARLIN WAYNE;GOMEZ
VALENTINA
ARM;RIOCREUX PETER
ANDREW;INGRAM GRAEME
LESLIE
ARM;LUTZ DAVID RAYMOND
Copyright 2016 Innovation Research Corporation
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No.
公報番号
262
US8456214B2
263
US8453073B1
264
US8463960B2
265
US8458532B2
266
US8456939B2
267
US8451039B2
出願日
タイトル (英語)
出願人
State retention circuit and method of operation of such a ARM;FREDERICK JR. MARLIN
2010/11/12
circuit
WAYNE
Method of mask generation for integrated circuit
ARM;DWIVEDI
2012/3/13
fabrication
SHRISAGAR;SAWHNEY PUNEET
ARM;MANNAVA PHANINDRA
KUMAR;JALAL
2011/8/8 Synchronisation of data processing systems
JAMSHED;PRASADH
RAMAMOORTHY GURU;FILIPPO
MICHAEL ALAN
ARM;JAUBERT JOCELYN
Error handling mechanism for a tag memory within
FRANCOIS ORION;BEGON
2010/10/27
coherency control circuitry
FLORENT;TEYSSIER MELANIE
EMANUELLE LUCIE
2010/11/22 Voltage regulation circuitry
ARM;PRABHAT PRANAY
ARM;MYERS JAMES
EDWARD;BIGGS JOHN
2011/5/13 Apparatus for storing a data value in a retention mode
PHILIP;FLYNN DAVID
WALTER;TRADOWSKY CARSTEN
審査･権利状況被引用回数外国出願
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3
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0
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1
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ARM;BIGGS JOHN PHILIP;MYERS
Integrated circuit, method of generating a layout of an
JAMES EDWARD;HOWARD
2011/5/13 integrated circuit using standard cells, and a standard cell
登録記録あり
DAVID WILLIAM;FLYNN DAVID
library providing such standard cells
WALTER;TRADOWSKY CARSTEN
0
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3
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1
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0
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3
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3
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4
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268
US8451026B2
269
US8418187B2
270
US8418175B2
2009/2/12
271
US8417923B2
2010/6/1
272
US8417920B2
2007/12/21
273
US8417915B2
2005/8/5
274
US8407540B2
2010/6/15
Virtualization software migrating workload between
2010/3/1 processing circuitries while making architectural states
available transparent to operating system
ARM;GREENHALGH PETER
RICHARD;GRISENTHWAITE
RICHARD ROY
ARM;MANSELL DAVID
Data processing apparatus and method for controlling
HENNAH;GRISENTHWAITE
access to secure memory by virtual machines executing
RICHARD ROY;BILES STUART
on processing circuirty
DAVID
ARM;WILLIAMS MICHAEL
Data processing apparatus having trace and prediction
JOHN;HORLEY JOHN
logic
MICHAEL;ASHFIELD EDMOND
JOHN SIMON
ARM;STEVENS ASHLEY
Management of speculative transactions
MILES;CROXFORD DAREN
ARM;GILDAY DAVID
Alias management within a virtually indexed and
MICHAEL;GRISENTHWAITE
physically tagged cache memory
RICHARD ROY
Low overhead circuit and method for predicting timing
ARM;CHANDRA VIKAS
errors
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
Error recover within processing stages of an integrated
circuit
275
US8407537B2
2010/10/13
276
US8407529B2
2011/12/29 Trace synchronization
277
US8407025B2
2009/2/25
278
US8397193B2
2009/4/17 Proprietary circuit layout identification
279
US8395440B2
280
US8395433B2
2010/4/20 Input-output device protection
281
US8390328B2
2011/5/13
282
US8386890B2
2009/9/11 Error correction for multilevel flash memory
2010/11/23
Operating parameter control of an apparatus for
processing data
Apparatus and method for controlling power gating in an
integrated circuit
Supplying a clock signal and a gated clock signal to
synchronous elements
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;FLAUTNER
KRISZTIAN;AUSTIN TODD
MICHAEL;BLAAUW DAVID
THEODORE;MUDGE TREVOR
NIGEL
ARM;HORLEY JOHN
MICHAEL;SWAINE ANDREW
BROOKFIELD;HOULIHANE
THOMAS SEAN;WOODHOUSE
SHELDON JAMES;WILLIAMS
MICHAEL JOHN
ARM;THE REGENTS OF THE
UNIVERSITY OF
MICHIGAN;BLAAUW DAVID
THEODORE;SYLVESTER DENNIS
MICHAEL;FICK DAVID
ALAN;BILES STUART
DAVID;WIECKOWSKI MICHAEL
JOHN;HANSON SCOTT
MCLEAN;CHEN GREGORY
KENGHO
ARM;TING ALBERT LI MING;SU
SHUN-PIAO
ARM;SANDHU BAL S.;IDGUNJI
SATCHIN SATISH;FLYNN DAVID
WALTER
ARM;RIEN MIKAEL;DUBY JEANCLAUDE
ARM;MYERS JAMES
EDWARD;FLYNN DAVID
WALTER;AITKEN ROBERT
CAMPBELL;FREDERICK JR.
MARLIN WAYNE
ARM;WEZELENBURG MARTINUS
CORNELIS;CONWAY THOMAS
KELSHAW
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No.
公報番号
283
US8386754B2
284
US8381162B2
285
US8381083B2
286
US8378861B2
287
US8375196B2
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
ARM;BLASCO ALLUE
CONRADO;WILLIAMSON DAVID
Renaming wide register source operand with plural short
JAMES;HARDAGE JAMES
2009/6/24 register source operands for select instructions to detect
登録記録あり
NOLAN;HARRIS GLEN
dependency fast with existing mechanism
ANDREW;MCDONALD ROBERT
GREGORY
Method of adapting a layout of a standard cell of an
2010/10/5
ARM;PELLOIE JEAN-LUC
登録記録あり
integrated circuit
ARM;WEZELENBURG MARTINUS
Error control coding for single error correction and
2009/10/22
登録記録あり
CORNELIS;CONWAY THOMAS
double error detection
KELSHAW
2010/11/29
Storage of probability values for contexts used in
arithmetic coding
Vector processor with vector register file configured as
matrix of data cells each selecting input from generated
2010/1/19
vector data or data from other cell via predetermined
rearrangement path
288
US8375170B2
2010/2/12 Apparatus and method for handling data in a cache
289
US8374098B2
2009/11/3 Check data encoding using parallel lane encoders
290
US8230277B2
2011/4/4
291
US8219885B2
2009/4/7
292
US8185812B2
2006/12/11
293
US8185786B2
2010/10/13
294
US8145960B2
2007/7/2
295
US8103922B2
2011/6/16 Error detection in precharged logic
296
US8060814B2
2009/8/21
297
US7945811B2
Storage of data in data stores having some faulty storage
locations
Error detecting and correcting mechanism for a register
file
Single event upset error detection within an integrated
circuit
Error recovery within processing stages of an integrated
circuit
Storage of data in data stores having some faulty storage
locations
Error recovery within processing stages of an integrated
circuit
Low power, high reliability specific compound functional
2008/10/2
units
5
○
4
○
2
○
ARM;BERKEMAN ANDERS;SYMES
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DOMINIC HUGO
0
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ARM;BJöRKLUND
ANDREAS;PERSSON
ERIK;HUGOSSON OLA
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1
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0
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4
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0
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2
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11
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3
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3
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0
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4
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登録記録あり
0
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ARM;LAYCOCK CHRISTOPHER
WILLIAM;HARRIS ANTONY
JOHN;MATHEWSON BRUCE
JAMES;ROSE ANDREW
CHRISTOPHER;GRISENTHWAITE
RICHARD ROY
ARM;WEZELENBURG MARTINUS
CORNELIS;PENTON ANTONY
JOHN;WONG KEN YI
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
Copyright 2016 Innovation Research Corporation
これだけはチェック！重要出願リスト
共同出願
No.
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況被引用回数外国出願
298
US7900020B2
ARM;TEXAS INSTRUMENTS
ARM;THE REGENTS OF THE
UNIVERSITY OF MICHIGAN
登録記録あり
4
○
299
US7701240B2
登録記録あり
4
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300
US7650551B2
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
21
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301
302
US7685404B2
US7533226B2
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
0
12
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○
303
US7512820B2
2006/9/13
Performance level selection in a data processing system
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
by combining a plurality of performance requests
9
○
304
US7401273B2
305
US7337356B2
306
US7320091B2
307
308
309
US7310755B2
US7343482B2
US7318143B2
2005/2/4 Recovery from errors in a data processing apparatus
Systematic and random error detection and recovery
2004/7/23
within processing stages of an integrated circuit
Error recovery within processing stages of an integrated
2005/4/21
circuit
2004/2/18 Data retention latch provision within integrated circuits
2005/1/31 Program subgraph identification
2005/1/28 Reuseable configuration data
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
26
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
34
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ARM;UNIVERSITY OF MICHIGAN 登録記録あり
42
○
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
24
18
3
○
○
○
310
US7321942B2
Performance counter for adding variable work increment
ARM;UNIVERSITY OF MICHIGAN 登録記録あり
value that is dependent upon clock frequency
22
○
311
US7278080B2
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44
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312
US7260694B2
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8
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313
US7263015B2
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4
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314
US7162661B2
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38
○
315
US7194385B2
登録記録あり
26
○
316
US7131015B2
登録記録あり
31
○
317
US7072229B2
登録記録あり
0
○
318
US7055007B2
登録記録あり
42
○
2008/1/25 Correction of incorrect cache accesses
Integrated circuit with error correction mechanisms to
2005/12/13
offset narrow tolerancing
Error detection and recovery within processing stages of
2007/8/16
an integrated circuit
2007/6/5 Program subgraph identification
2006/2/14 Data processor memory circuit
2003/10/20
Error detection and recovery within processing stages of
ARM;UNIVERSITY OF MICHIGAN
an integrated circuit
2006/9/26 Data processor memory circuit
ARM;UNIVERSITY OF MICHIGAN
ARM;THE REGENTS OF THE
2005/11/7 Address decoding
UNIVERSITY OF MICHIGAN
Systematic and random error detection and recovery
2004/2/18
ARM;UNIVERSITY OF MICHIGAN
within processing stages of an integrated circuit
2003/10/20 Performance level setting of a data processing system
ARM;UNIVERSITY OF MICHIGAN
Performance level selection in a data processing system
2003/10/20 using a plurality of performance request calculating
ARM;UNIVERSITY OF MICHIGAN
algorithms
Memory system having fast and slow data reading
ARM;THE REGENTS OF THE
2005/6/13
mechanisms
UNIVERSITY OF MICHIGAN
2003/4/10 Data processor memory circuit
ARM;UNIVERSITY OF MICHIGAN
2003/3/20
Copyright 2016 Innovation Research Corporation
注目度の高い特許出願がわかる！～被引用回数TOP10～
被引用順位
公報番号
出願日
タイトル (英語)
出願人
審査･権利状況
被引用回数
1
US6064626A 1998/7/31
Peripheral buses for integrated circuit
ARM
登録記録あり
153
2
US6002881A 1997/9/17
Coprocessor data access control
ARM
登録記録あり
118
Coprocessor opcode division by data type
ARM
登録記録あり
117
Apparatus and method for image data processing of pixel data in raster
lines
ARM
登録記録あり
101
Executing debug instructions
ARM
登録記録あり
92
Cache control circuit having a pseudo random address generator
ARM
登録記録あり
92
Testing compliance of a device with a bus protocol
ARM
登録記録あり
74
Tracing multiple data access instructions
ARM
登録記録あり
71
Breakpoint logic unit, debug logic and breakpoint method for a data
processing apparatus
ARM
登録記録あり
68
3
4
5
5
7
8
9
US6247113B
1998/5/27
1
US6259459B
1998/7/1
1
US6321329B
1999/5/19
1
US5875465A 1997/4/3
US6876941B
2002/2/28
2
US7080289B
2001/10/10
2
US7334161B
2004/4/30
2
10
US7162590B
2004/3/1
2
Memory bus within a coherent multi-processing system having a main
portion and a coherent multi-processing portion
ARM
登録記録あり
67
10
US6411957B
1999/6/30
1
System and method of organizing nodes within a tree structure
ARM
登録記録あり
67
10
US5918042A 1997/1/10
Dynamic logic pipeline control
ARM
登録記録あり
67
被引用回数の多い出願について
●審査官によって引用された回数の多い出願は、注目度の高い特許出願である可能性があり、基本技術把握の観点から、必ずチェックしておく必要がある。